DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 348

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.10 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a
TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Rev. 3.00 Sep. 28, 2009 Page 302 of 910
REJ09B0350-0300
Figure 10.50 Conflict between Buffer Register Write and Input Capture
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 10.51 Conflict between Overflow and Counter Clearing
φ
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV
H'FFFF
Disabled
Buffer register write cycle
M
T1
Buffer register
address
N
T2
H'0000
M
N

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