DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 654
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 19 LPC Interface (LPC)
• LADR2L
• Host select register
Note:
Rev. 3.00 Sep. 28, 2009 Page 608 of 910
REJ09B0350-0300
Bit
7
6
5
4
3
2
1
0
Bits 5 to 3
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bit Name
Bit 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
* When channel 2 is used, the content of LADR2 must be set so that the addresses for
channels 1, 3, 4, and SCIF are different.
Initial
Value
0
1
1
0
0
0
1
0
I/O Address
Bit 2
0
1
0
1
Slave Host Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 1 and 0
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel 2 Address Bits 7 to 3
Set the LPC channel 2 host address.
Reserved
This bit is ignored when an address match is decided.
Channel 2 Address Bits 1 and 0
Set the LPC channel 2 host address.
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
Host Select Register
IDR2 write (data)
IDR2 write (command)
ODR2 read
STR2 read
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