DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 629

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.4.10 First KCLK Falling Interrupt
An interrupt can be generated by detecting the first falling edge of KCLK on reception and
transmission. Software standby mode and watch mode can be cancelled by a first KCLK falling
interrupt.
• Reception
• Transmission
• Determining interrupt generation
KCLK
KD
RXCR3
to RXCR0
Interrupt
internal
signal
When both KBIOE and KBE are set to 1, KCIF is set after the first falling edge of KCLK has
been detected.
At this time, if KCIE is set to 1, the CPU is requested an interrupt.
KCIF is set at the same time when the RXCR3 to RXCR0 bits in KBCRL are incremented
from B'0000 to B'0001.
When both KBIOE and KBTS are set to 1, the KCIF is set after the first falling edge of KCLK
has been detected.
At this time, if KCIE is set to 1, the CPU is requested an interrupt.
KCIF is set at the same time when the TXCR3 to TXCR0 bits in KBCR2 are incremented from
B'0000 to B'0001.
By checking the KBE, KBTS, and KBTE bits, it can be determined whether the first KCLK
falling interrupt is occurred during reception or transmission.
During reception: KBE = 1
During transmission: KBTS = 1 or KBTE = 1 (Check KBTE = 1 because the KBTS is
automatically cleared after transfer has been completed.)
Interrupt generated
0000
Start bit
1
0001
Figure 18.15 Timing of First KCLK Interrupt
(a) Reception
2
0010
0
3
1
KCLK
KD
TXCR3
to TXCR0
Interrupt
internal
signal
Section 18 Keyboard Buffer Control Unit (PS2)
I/O inhibit
Rev. 3.00 Sep. 28, 2009 Page 583 of 910
Interrupt generated
Start bit
0000
(b) Transmission
1
0001
0
REJ09B0350-0300
2
0010
1