DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 491

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[3]
No
No
Read receive data in RDR and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Overrun error processing
Figure 15.19 Sample Serial Reception Flowchart
All data received?
Error processing
Start reception
End reception
Initialization
ORER = 1
RDRF = 1
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
[6]
Section 15 Serial Communication Interface (SCI)
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI status check and receive data
[5] Serial reception continuation
Note:
The RxD pin is automatically
designated as the receive data input
pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to
1 can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
Rev. 3.00 Sep. 28, 2009 Page 445 of 910
Do not write to SMR, SCR, BRR,
and SDCR from the start to the
end of reception except the
process of [6].
REJ09B0350-0300