DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 279

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.6.
Table 9.6 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
Figure 9.5 Output Waveform (OS = 1, DADR corresponds to T
t
t
t
H1
t
t
t
f1
H1
Duty cycle of base pulse
H1
f1
H1
Figure 9.6 D/A Data Register Configuration when CFS = 1
= t
= t
+ t
+ t
t
f1
t
f2
f1
f2
H2
H2
= t
= t
+ t
+ t
f3
f3
H3
= ··· = t
H3
= ··· = t
+ ··· + t
+ ··· + t
t
f255
H2
t
f63
H2
(b) CFS = 1 [base cycle = resolution (T) × 256]
(a) CFS = 0 [base cycle = resolution (T) × 64]
H255
H63
DA8
= t
= t
t
t
f2
f2
f64
f256
+ t
+ t
= T× 256
H64
H256
DA7
= T× 64
= T
= T
1 conversion cycle
1 conversion cycle
H
H
DA6
t
H3
t
H3
DA5
Location of additional pulses
DA4
t
H255
t
H63
Rev. 3.00 Sep. 28, 2009 Page 233 of 910
t
DA3
f255
t
f63
Section 9 14-Bit PWM Timer (PWMX)
DA2
t
H256
t
DA1
H64
t
f256
t
f64
DA0
REJ09B0350-0300
H
)
CFS
1
1