DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 711

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
20.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 20.2 shows the A/D conversion timing. Table 20.4 indicates
the A/D conversion time.
As indicated in figure 20.2, the A/D conversion time (t
(t
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values shown in table 20.4 become those for the first conversion time. The
second and subsequent conversion times are listed in table 20.5. In either case, bits CKS1 and
CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the
A/D conversion characteristics.
SPL
). The length of t
Input Sampling and A/D Conversion Time
D
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
(2):
t
t
t
D
SPL
CONV
varies depending on the timing of write to ADCSR. The total conversion
:
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 20.2 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) passes after the ADST bit in ADCSR is set to
t
CONV
CONV
) includes t
Rev. 3.00 Sep. 28, 2009 Page 665 of 910
D
and the input sampling time
Section 20 A/D Converter
REJ09B0350-0300

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