DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 753

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1)
Parts of the procedure program that is made by the user, like download request,
programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM.
Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on-
chip program and procedure program do not overlap. Figure 22.11 shows the area of the on-chip
program to be downloaded.
On-Chip RAM Address Map when Programming/Erasing is Executed
Figure 22.11 RAM Map when Programming/Erasing is Executed
Unusable area during
programming/erasing
Area to be
downloaded
(size: 3 kbytes)
programming end program
Area that can be used
erasing program entry
Initialization program
(Return value: 1 byte)
programming end/
System use area
erasing program
programming +
Initialization +
Initialization +
Programming/
(15 bytes)
by user
entry
DPFR
or
FTDAR setting
FTDAR setting + address 16
FTDAR setting + address 32
FTDAR setting + 3 kbytes
H'FFEFFF
Rev. 3.00 Sep. 28, 2009 Page 707 of 910
Section 22 Flash Memory
REJ09B0350-0300