DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 737

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.2
The programming/erasing interface parameters specify the operating frequency, storage place for
program data, start address of programming destination, and erase block number, and exchanges
the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the
on-chip RAM area. The initial values of programming/erasing interface parameters are undefined
at a power-on reset or a transition to software standby mode.
Since registers of the CPU except for R0L are saved in the stack area during download of an on-
chip program, initialization, programming, or erasing, allocate the stack area before performing
these operations (the maximum stack size is 128 bytes). The return value of the processing result
is written in R0L. The programming/erasing interface parameters are used in download control,
initialization before programming or erasing, programming, and erasing. Table 22.6 shows the
usable parameters and target modes. The meaning of the bits in the flash pass and fail result
parameter (FPFR) varies in initialization, programming, and erasure.
Table 22.6 Parameters and Target Modes
Note:
(a)
The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-
chip RAM area to download the on-chip program is the 4-kbyte area starting from the start address
specified by FTDAR. Download is set by the programming/erasing interface registers, and the
download pass and fail result parameter (DPFR) indicates the return value.
Parameter
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
Download Control
* A single byte of the start address of the on-chip RAM specified by FTDAR
Programming/Erasing Interface Parameters
Download
O
⎯
⎯
⎯
⎯
⎯
Initialization
⎯
O
O
⎯
⎯
⎯
Programming
⎯
O
⎯
O
O
⎯
Erasure
⎯
O
⎯
⎯
⎯
O
Rev. 3.00 Sep. 28, 2009 Page 691 of 910
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Section 22 Flash Memory
REJ09B0350-0300
Allocation
On-chip RAM*
R0L of CPU
ER0 of CPU
ER1 of CPU
ER0 of CPU
ER0 of CPU