DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 810

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 23 Clock Pulse Generator
23.2
The duty correction circuit generates the system clock (φ) by correcting the duty of the clock
output from the oscillator.
23.3
The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the
subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin.
Figure 23.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin.
When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the
pin to 0. The EXCL pin is specified as an input pin by clearing the EXCLS bit in PTCNT0 to 0.
The ExEXCL pin is specified as an input pin by setting the EXCLS bit in PTCNT0 to 1. The
subclock input is enabled by setting the EXCLE bit in LPWRCR to 1.
Subclock input conditions are shown in table 23.5. When the subclock is not used, subclock input
should not be enabled.
Table 23.5 Subclock Input Conditions
Rev. 3.00 Sep. 28, 2009 Page 764 of 910
REJ09B0350-0300
Item
Subclock input pulse width
low level
Subclock input pulse width
high level
Subclock input rising time
Subclock input falling time
Duty Correction Circuit
Subclock Input Circuit
Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin
PE0/ExEXCL
P96/EXCL
Symbol
t
t
t
t
EXCLL
EXCLH
EXCLr
EXCLf
Min.
(PTCNT0)
EXCLS
VCC = 3.0 to 3.6 V
Typ.
15.26
15.26
(LPWRCR)
EXCLE
Max.
10
10
Subclock
Unit
μs
μs
ns
ns
Test Conditions
Figure 23.8

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