DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 66

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 20 of 910
REJ09B0350-0300
Type
Interrupts
H-UDI
8-bit
timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y)
Symbol
NMI
IRQ15 to
IRQ0
ExIRQ15
to
ExIRQ6
ETRST*
ETMS
ETDO
ETDI
ETCK
TMO0
TMO1
TMOX
TMOY
TMI0
TMI1
TMIX
TMIY
2
11
17,
19 to 21,
47 to 50,
85, 84,
135 to 133,
24 to 22
51 to 58,
12, 10
27
28
29
30
31
137
3
47
48
136
2
58
57
TFP-144V BP-176V TLP-145V I/O
F4
G2, H2,
J4, J3,
N6, R6,
P6, M7,
J13, J12,
B6, A6,
C6, K4,
J2, J1
R7, P7,
M8, R8,
P8, N9,
R9, P9,
F3, E1
L1
L2
L4
M1
M2
B5
B1
N6
R6
A5
C3
P9
R9
Pin No.
E3
F1, G4,
H4, G1,
L5, M6,
N5, K5,
H12, J11,
C6, B5,
A6, H2,
G3, J4
L6, M7,
N6, K6,
K7, K8,
N7, M8,
F2, E2
H3
K4
J1
K2
A5
C2
L5
M6
D4
A1
M8
N7
J3
Input
Input
Input
Input
Input
Output
Input
Input
Output Waveform output pins with output
Input
Name and Function
Nonmaskable interrupt request input
pin.
These pins request a maskable
interrupt.
To which pin an IRQ interrupt is
input can be selected from the IRQn
and ExIQRn pins.
(n = 15 to 6)
Interface pins for emulator
Reset by holding the ETRST pin to
low level regardless of the H-UDI
activation. At this time, the ETRST
pin should be held low level for 20
clocks of ETCK. Then, to activate
the H-UDI, the ETRST pin should be
set to high level and the pins ETCK,
ETMS, and ETDI should be set
appropriately. In the normal
operation without activating the H-
UDI, pins ETCK, ETMS, ETDI, and
ETDO should be pulled up to high
level. The ETRST pin is pulled up
inside the chip.
compare function.
Counter event input and count reset
input pins.

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