DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 706

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 20 A/D Converter
20.3.2
ADCSR controls A/D converter operation.
Note:
Rev. 3.00 Sep. 28, 2009 Page 660 of 910
REJ09B0350-0300
Bit
7
6
5
4
Bit Name Initial Value
ADF
ADIE
ADST
* Only 0 can be written to clear the flag.
A/D Control/Status Register (ADCSR)
0
0
0
0
R/W
R/(W)*
R/W
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
[Clearing condition]
When 0 is written after reading ADF = 1
A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1.
A/D Start
When this bit is cleared to 0, A/D conversion stops
and enters wait state. When this bit is set to 1 by a
conversion start trigger from software, TPU, or TMR,
A/D conversion starts. This bit remains set to 1 during
A/D conversion. In single mode, this bit is
automatically cleared to 0 when conversion on the
specified channel ends. In scan mode, conversion
continues sequentially on the specified channels until
this bit is cleared to 0 by a reset, or software.
Reserved
This bit is always read as 0 and cannot be modified.
When A/D conversion ends in single mode
When A/D conversion ends on all channels
specified in scan mode

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