DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 360
![IC H8S/2117 MCU FLASH 145TFLGA](/photos/12/20/122098/df2117vlp20v_sml.jpg)
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 360 of 960
- Download datasheet (6Mb)
Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 3.00 Sep. 28, 2009 Page 314 of 910
REJ09B0350-0300
Bit
4
3
2
1
0
Bit Name
IEDG
TCMMDS
CKS2
CKS1
CKS0
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Input Edge Select
In timer mode, selects the falling or rising edge of the
TCMCYI input for use in input capture, in combination with
the value of the POCTL bit.
In cycle measurement mode, selects the falling or rising
edge of the TCMCYI input for use in measurement, in
combination with the value of the POCTL bit.
POCTL = 0
0: Selects the rising edge of the TCMCYI input
1: Selects the falling edge of the TCMCYI input
POCTL = 1
0: Selects the falling edge of the TCMCYI input
1: Selects the rising edge of the TCMCYI input
TCM Mode Select
Selects the TCM operating mode.
0: Timer mode
1: Cycle measurement mode
Clock Select 2, 1, 0
Selects the clock signal for input to TCMCNT.
Note: Modify this bit when CST = 0 and TCMMDS = 0
000: Count φ/2 internal clock
001: Count φ/8 internal clock
010: Count φ/16 internal clock
011: Count φ/32 internal clock
100: Count φ/64 internal clock
101: Count φ/128 internal clock
110: Count φ/256 internal clock
111: Count external clock (select the external clock edge
The TCM provides compare match and input capture
facilities.
Setting this bit to 1 starts counting by TCMCNT. TCMCNT
should be initialized to H'0000. Clear the CST in TCMCR
to 0 before setting to cycle measurement mode.
with CKSEG in TCMCSR.)
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