DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 697

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 19.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used
Host Interrupt
HIRQi
(i = 1 to 15)
No
No
Setting Condition
Internal CPU sets the corresponding
SERIRQ host interrupt request for the
SCIF in SIRQCR4 (for details, see the
description of SIRQCR4).
Changes in the SCIF input signal DCD are
detected.
Write 1 to IRQ1E1
Figure 19.8 HIRQ Flowchart (Example of Channel 1)
ODR1 write
transferred?
OBF1 = 0?
All bytes
Yes
Yes
Slave CPU
SERIRQ IRQ1 output
SERIRQ IRQ1
source clear
Rev. 3.00 Sep. 28, 2009 Page 651 of 910
Clearing Condition
Reads FMSR and clears the DDCD
bit in FMSR
Hardware operation
Software operation
Section 19 LPC Interface (LPC)
Interrupt initiation
Master CPU
ODR1 read
REJ09B0350-0300