DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 385

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bit
5
4
3
Bit Name
CPSPE
IEDG
TDPMDS
Initial
Value R/W
0
0
0
R/W
R/W
R/W
Description
Input Capture Stop Enable
Controls whether counting up by TDPCNT and input-
capture operation stop or continue when any of the
TPDMXOVF, TPDMNUDF, TWDMXOVF, and TWDMNUDF
flags is set to 1 in cycle measurement mode. This bit does
not affect operation in timer mode.
0: Counting up and input-capture operation continue when
1: Counting up and input-capture operation stop when any
Input Edge Select
In timer mode, in combination with the value of the POCTL
bit, selects the falling or rising edge of the TDPCYI input for
capturing input.
In cycle measurement mode, this bit does not affect
operation.
When POCTL = 0
0: The falling edge of TDPCYI input is selected
1: The rising edge of TDPCYI input is selected
When POCTL = 1
0: The rising edge of TDPCYI input is selected
1: The falling edge of TDPCYI input is selected
TDP Mode Select
Selects the TDP operating mode.
0: Timer mode
1: Cycle measurement mode
any of the flags is set to 1.
of the flags is set to 1.
In timer mode, the operating mode is input capture and
compare match.
Setting this bit to 1 starts counting by TDPCNT. Clear the
CST bit in TDPCR1 to initialize TDPCNT to H'0000
before setting cycle measurement mode.
Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 339 of 910
REJ09B0350-0300

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