DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 23

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Item
22.8.4 Storable Areas for On-
Chip Program and Program Data
Table 22.9 Executable Memory
MAT
Page Revision (See Manual for Details)
719
720
Description amended
• In an operating mode in which the external address
• The flash memory is not accessible during
• After programming/erasing starts, access to the
• Switching of the MATs by FMATS should be
Table amended
Note added
Note * Programming/Erasing is possible to the User
Processing Contents
Programming
Erasing
space is not accessible, such as single-chip mode,
the required procedure programs
transferred to the on-chip RAM before
programming/erasing starts (download result is
determined).
programming/erasing. Programming/erasing is
executed by the program downloaded to the on-chip
RAM. Therefore, the procedure program that
initiates operation
RAM other than the flash memory.
flash memory should be inhibited until FKEY is
cleared. The reset input state (period of RES = 0)
must be set to at least 100 μs when the operating
mode is changed and the reset start executed on
completion of programming/erasing. Transitions to
the reset state are inhibited during
programming/erasing. When the reset signal is
input, a reset input state (period of RES = 0) of at
least 100 μs is needed before the reset signal is
released.
required when programming/erasing of the user
MAT is operated in user boot mode. The program
that switches the MATs should be executed from
the on-chip RAM.
(For details, see section 22.10, Switching between
User MAT and User Boot MAT.)
Make sure you know which MAT is currently
selected when witching them.
Mat.
User Program Mode
See table 22.10.
See table 22.11.
Rev. 3.00 Sep. 28, 2009 Page xxi of xliv
should be stored in the on-chip
Operating Mode
User boot Mode*
See table 22.12
See table 22.13
should be
REJ09B0350-0300

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