DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 599

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.8
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 17.21 shows a block diagram of the noise canceller.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
17.4.9
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in ICRES or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 17.3.7, I
Control Initialization Register (ICRES).
(1)
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
The following items are not initialized:
output, etc.)
Scope of Initialization
Noise Canceller
Initialization of Internal State
SCL or
SDA input
signal
Sampling
clock
Figure 17.21 Block Diagram of Noise Canceller
Sampling clock
System clock
D
cycle
Latch
C
Q
D
Latch
C
Q
Rev. 3.00 Sep. 28, 2009 Page 553 of 910
detector
Match
Section 17 I
Internal
SCL or
SDA
signal
2
C Bus Interface (IIC)
REJ09B0350-0300
2
C Bus