DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 602

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
Table 17.9 I
Note:
4. The I
Table 17.10 Permissible SCL Rise Time (t
Rev. 3.00 Sep. 28, 2009 Page 556 of 910
REJ09B0350-0300
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
IICX t
0
1
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 17.10.
7.5 t
17.5 t
cyc
* 6t
Indication
2
C bus interface specification for the SCL rise time t
cyc
cyc
2
C Bus Interface (IIC)
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12t
Standard mode
High-speed mode 300
Standard mode
High-speed mode 300
cyc
when 1.
I
Specification
(Max.)
1000
1000
2
2
C Bus
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
sr
) Values
sr
(the time for SCL to go from low to V
2
C bus interface, the high period of SCL is
φ =
8 MHz
937
300
1000
300
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
12t
3t
SCLO
SCLLO
SCLL
cyc
cyc
cyc
Time Indication [ns]
SCLO
SCLO
SCLO
SCLO
SCLO
*)
– (6t
to 256t
sr
– 3t
is 1000 ns or less (300 ns for high-
– 1t
– 1t
+ 2t
φ =
10 MHz
750
300
1000
300
cyc
cyc
cyc
cyc
cyc
or
cyc
φ =
16 MHz
468
300
1000
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
See figure
26.23 (for
reference)
IH
φ =
20 MHz
375
300
875
300
) exceeds