R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 140

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 111 of 573
Figure 9.7
FMR0 Register
(flash memory
(flash memory
FMSTP Bit
operates)
stops)
Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed.
To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the VCA20 bit in the VCA2 register, as shown in Figure 9.7.
The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU
exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits
CM16 and CM17 in the CM1 register automatically change.
0
1
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
low consumption disabled)
low consumption enabled)
low consumption enabled)
low consumption disabled
Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is
Executed
VCA2 Register
(internal power
(internal power
(internal power
(internal power
VCA20 Bit
Wait mode
0
1
0
1
Interrupt request generation
stabilization time
Stabilization Time
Internal power
100 µs (max.)
Internal Power
100 µs (max.)
100 µs (max.)
T0
0 µs
0 µs
(T0)
Period of system clock
Period of system clock
activation sequence
× 1 cycle + 60 µs
Activation (T1)
Flash memory
Flash Memory
Time until
× 1 cycle
(max.)
T1
Period of CPU clock
Same as above
restart sequence
Supply (T2)
CPU Clock
× 2 cycles
Time until
CPU clock
T2
Period of CPU clock
Interrupt sequence
Same as above
Sequence (T3)
× 20 cycles
Time for
Interrupt
9. Clock Generation Circuit
T3
The total of T0
to T3 is the time
from wait mode to
interrupt routine
execution.
Remarks