R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 154

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 125 of 573
Figure 11.2
11.1.5
Table 11.1
Note:
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1,
Voltage monitor 2
Address break
(Reserved)
Reset
11.1.5.1
1. Do not use these interrupts. They are provided exclusively for use by development tools.
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 11.2 shows an Interrupt Vector.
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 11.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 29.3 Functions to Prevent Flash Memory from being Rewritten.
Interrupt Source
Interrupts and Interrupt Vectors
(1)
Vector address (H)
Fixed Vector Tables
Fixed Vector Tables
Interrupt Vector
Vector address (L)
(1)
0FFDCh to 0FFDFh Interrupt with
0FFE8h to 0FFEBh
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFE0h to 0FFE3h Interrupt with
0FFE4h to 0FFE7h If the content of address
0FFFCh to 0FFFFh
Vector Addresses
Address (L) to (H)
MSB
0 0 0 0
0 0 0 0
Middle-order address
Low-order address
UND instruction
INTO instruction
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Remarks
High-order address
0 0 0 0
R8C/Tiny Series
Software Manual
11.6 Address Match
14. Watchdog Timer
9. Clock Generation Circuit
6. Voltage Detection Circuit
5. Resets
Interrupt
LSB
Reference
11. Interrupts