R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 174

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 145 of 573
As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I
bus interface interrupt, and flash memory interrupt are controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple
interrupt request sources, the following differences from other maskable interrupts apply:
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Refer to chapters of the individual peripheral functions (19. Timer RC, 24. Synchronous Serial Communication
Unit (SSU), 25. I
For the interrupt control register, refer to 11.3 Interrupt Control.
When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR
bit is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, the IR bit is not set to 0 even if 0 is written to this bit.
Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, use the status register to determine which request source
causes an interrupt.
2
C bus Interface, and 29. Flash Memory) for the status register and enable register.
11. Interrupts
2
C