R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 214
R5F21324CNSP#U0
Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet
1.R5F21321CDSPU0.pdf
(605 pages)
Specifications of R5F21324CNSP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 214 of 605
- Download datasheet (6Mb)
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 185 of 573
15.3.10.4 SSU/I
15.3.10.5 SSU/I
When the DTC activation source is SSU/I
using a data transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in
SSRDR/ICDRR register) by reading the SSRDR register/ the ICDRR register. If an interrupt source for receive
data full is subsequently generated, the DTC acknowledges it as the activation source.
When the DTC activation source is SSU/I
register using a data transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not
transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT
register. If an interrupt source for transmit data empty is subsequently generated, the DTC acknowledges it as
the activation source.
2
2
C bus Receive Data Full
C bus Transmit Data Empty
2
2
C bus receive data full, read the SSRDR register/the ICDRR register
C bus transmit data empty, write to the SSTDR register/the ICDRT
15. DTC
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