MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XEP100MAL
Manufacturer:
FREESCALE
Quantity:
4 500
Part Number:
MC9S12XEP100MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XEP100MAL
Manufacturer:
FREESCALE
Quantity:
4 500
Part Number:
MC9S12XEP100MAL
Manufacturer:
NXP USA Inc.
Quantity:
57 240
Part Number:
MC9S12XEP100MAL
Manufacturer:
NXP
Quantity:
180
MC9S12XEP100
Reference Manual
Covers MC9S12XE Family
HCS12X
Microcontrollers
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
MC9S12XEP100RMV1
Rev. 1.23
09/2010
freescale.com

Related parts for MC9S12XEP100MAL

MC9S12XEP100MAL Summary of contents

Page 1

MC9S12XEP100 Reference Manual Covers MC9S12XE Family HCS12X Microcontrollers Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States ...

Page 2

To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: http://freescale.com/ This document contains information for the complete S12XE-Family and ...

Page 3

... KByte Flash Module (S12XFTM256K2V1 889 MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 4

... Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 MC9S12XE-Family Reference Manual , Rev. 1.23 4 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 5

... Blank Page Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev. 1.23 ...

Page 6

... Blank Page MC9S12XE-Family Reference Manual , Rev. 1.23 6 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 7

... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 8

... Port M Pull Device Enable Register (PERM 134 MC9S12XE-Family Reference Manual , Rev. 1.23 8 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 9

... Port R Data Register (PTR 164 2.3.86 Port R Input Register (PTIR 164 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 10

... Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 MC9S12XE-Family Reference Manual , Rev. 1.23 10 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 3 Freescale Semiconductor ...

Page 11

... Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 12

... MC9S12XE-Family Reference Manual , Rev. 1.23 12 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 6 Interrupt (S12XINTV2) Chapter 7 Freescale Semiconductor ...

Page 13

... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 14

... MC9S12XE-Family Reference Manual , Rev. 1.23 14 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 469 Freescale Semiconductor ...

Page 15

... IOC7 — Input Capture and Output Compare Channel 527 14.2.2 IOC6 — Input Capture and Output Compare Channel 527 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 12 — ...

Page 16

... MC9S12XE-Family Reference Manual , Rev. 1.23 16 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 15 Chapter 16 Freescale Semiconductor ...

Page 17

... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 18.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 18

... MC9S12XE-Family Reference Manual , Rev. 1.23 18 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 19 Chapter 20 Freescale Semiconductor ...

Page 19

... Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 21.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 21 MC9S12XE-Family Reference Manual Rev ...

Page 20

... MC9S12XE-Family Reference Manual , Rev. 1.23 20 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 22 Chapter 23 Freescale Semiconductor ...

Page 21

... KByte Flash Module (S12XFTM256K2V1) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 22

... MC9S12XE-Family Reference Manual , Rev. 1.23 22 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Chapter 26 Chapter 27 Freescale Semiconductor ...

Page 23

... KByte Flash Module (S12XFTM1024K5V2) 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 24

... MC9S12XE-Family Reference Manual , Rev. 1.23 24 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Appendix A Electrical Characteristics Freescale Semiconductor ...

Page 25

... D.2 Pinout explanations 1267 Detailed Register Address Map Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 26

... MC9S12XE-Family Reference Manual , Rev. 1.23 26 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 27

... MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 28

... IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation) MC9S12XE-Family Reference Manual , Rev. 1.23 28 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 29

... Five MSCAN (1 M bit per second, CAN 2 software compatible modules) — Five receive and three transmit buffers Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 30

... MC9S12XE-Family Reference Manual , Rev. 1.23 30 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 24 bus clock cycles Freescale Semiconductor ...

Page 31

... Supervisor state • User state Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev. 1.23 ...

Page 32

... PM3 RXCAN PM4 PM5 TXCAN RXCAN PM6 TXCAN PM7 RXD PL0 TXD PL1 RXD PL2 TXD PL3 PL4 RXD TXD PL5 RXD PL6 TXD PL7 RXD PJ0 TXD PJ1 PJ2 PJ3 SDA PJ4 SCL PJ5 RXCAN PJ6 TXCAN PJ7 Freescale Semiconductor ...

Page 33

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-1. Device Register Memory Map ...

Page 34

... Voltage regulator Reserved PWM (pulse-width modulator 8 channels) Reserved SCI6 (serial communications interface) SCI7 (serial communications interface) PIT (periodic interrupt timer) PIM (port integration module) XGATE Reserved TIM (timer module) Reserved NOTE Table 1-1 is not allocated to any module. Size (Bytes 1024 Freescale Semiconductor ...

Page 35

... MMC section. Figure 1-2. MC9S12XE100 Global Memory Map Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 36

... Freescale for import or sale in the United States prior to September 2010 RAM_LOW EE_LOW 0x0F_0000 0x13_F000 B3, B2, B1S, B1N, B0 0x0F_0000 0x13_F000 B3, B2, B1S, B1N, B0 0x0F_8000 0x13_F000 0x0F_C000 0x13_F000 Table 1-4. Within EEPROM resource range an address range exists Flash Blocks Registers 2K 2K B1N, B1S B1S, B0(128K) 2K Freescale Semiconductor ...

Page 37

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-3. XGATE Resources ...

Page 38

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 0x74_0000 0x78_0000 0x7A_0000 — — B1S B1S (64K) — — 0x7C_0000 0x7E_0000 — B0(128K) — B0 (64K) Freescale Semiconductor ...

Page 39

... Figure 1-3. XGATE Global Address Mapping Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 40

... MC9S12XE-Family Reference Manual , Rev. 1.23 40 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-6 shows the assigned part ID Freescale Semiconductor ...

Page 41

... Currently available as MC9S12XET256 die only 1.2 Signal Description Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-6 ...

Page 42

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 NOTE Appendix D Derivative Differences and Table 1-9. Pin-Out Summary for more Table 1-7. Port for Freescale Semiconductor ...

Page 43

... PL3 Figure 1-4. - Pin Assignments, 208 MAPBGA Package Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 44

... PAD16/AN16 104 PAD15/AN15 103 PAD07/AN07 102 PAD14/AN14 101 PAD06/AN06 100 PAD13/AN13 99 PAD05/AN05 98 PAD12/AN12 97 PAD04/AN04 96 PAD11/AN11 95 PAD03/AN03 94 PAD10/AN10 93 PAD02/AN02 92 PAD09/AN09 91 PAD01/AN01 90 PAD08/AN08 89 PAD00/AN00 88 VSS2 87 VDD 86 PD7/DATA7 85 PD6/DATA6 84 PD5/DATA5 83 PD4/DATA4 82 VDDX3 81 VSSX3 80 PA7/ADDR15 79 PA6/ADDR14 78 PA5/ADDR13 77 PA4/ADDR12 76 PA3/ADDR11 75 PA2/ADDR10 74 PA1/ADDR9 73 PA0/ADDR8 Freescale Semiconductor ...

Page 45

... Figure 1-6. MC9S12XE-Family Pin Assignments 112-pin LQFP Package Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 46

... Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family 8 80QFP VDDF 9 VSS1 PB0 16 PB1 17 PB2 18 PB3 19 PB4 20 60 VRH 59 VDDA1 58 PAD07/AN07 57 PAD06/AN06 56 PAD05/AN05 55 PAD04/AN04 54 PAD03/AN03 53 PAD02/AN02 52 PAD01/AN01 51 PAD00/AN00 50 VSS2 49 VDD 48 PA7 47 PA6 46 PA5 45 PA4 44 PA3 43 PA2 42 PA1 41 PA0 Freescale Semiconductor ...

Page 47

... THE STANDARD 80QFP BOND-OUT, COMPATIBLE WITH OTHER FAMILY MEMBERS. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 48

... MC9S12XE-Family Reference Manual , Rev. 1.23 48 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-8. Freescale Semiconductor ...

Page 49

... Available in 80QFP / 256K memory size only. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. The 9S12XET256 is the standard 256K/80QFP bondout, compatible with other family members. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 50

... PP[7:4] PR[7:0] MC9S12XE-Family Reference Manual , Rev. 1.23 50 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ( Freescale Semiconductor ...

Page 51

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 O O Table 1-9. Pin-Out Summary (Sheet (1) QFP ...

Page 52

... PB0 ADDR0 17 PB1 ADDR1 18 PB2 ADDR2 19 PB3 ADDR3 20 PB4 ADDR4 21 PB5 ADDR5 22 PB6 ADDR6 23 PB7 ADDR7 PC4 DATA12 3rd 4th 5th Func. Func. Func. VREGAPI ACC1 ACC0 TXD2 RXD2 CS3 IVD0 UDS IVD1 IVD2 IVD3 IVD4 IVD5 IVD6 IVD7 Freescale Semiconductor ...

Page 53

... T12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-9. Pin-Out Summary (Sheet ...

Page 54

... ADDR12 46 PA5 ADDR13 47 PA6 ADDR14 48 PA7 ADDR15 VSSX3 VDDX3 PD4 DATA4 PD5 DATA5 PD6 DATA6 PD7 DATA7 49 VDD 50 VSS2 3rd 4th 5th Func. Func. Func. MOSI1 TXD6 MISO1 RXD6 LDS EROMCTL WE IVD8 IVD9 IVD10 IVD11 IVD12 IVD13 IVD14 IVD15 Freescale Semiconductor ...

Page 55

... F13 107 83 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-9. Pin-Out Summary (Sheet ...

Page 56

... SS0 67 TEST 68 PJ7 KWJ7 69 PJ6 KWJ6 PJ5 KWJ5 PF0 CS0 PJ4 KWJ4 PF1 CS1 70 PM5 TXCAN2 3rd 4th 5th Func. Func. Func. TXCAN4 TXD3 RXCAN4 RXD3 TXCAN4 SCL0 TXCAN0 RXCAN4 SDA0 RXCAN0 SCL1 CS2 SDA1 CS0 TXCAN0 TXCAN4 SCK0 Freescale Semiconductor ...

Page 57

... Standard 80QFP only. NOTE that XEA256 80QFP is not compatible Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-9 ...

Page 58

... EROMON control Up Port E I/O, read/write Up Port E Input, maskable interrupt Up Port E input, non-maskable interrupt Up Port F I/O, interrupt, TXD of SCI3 Up Port F I/O, interrupt, RXD of SCI3 Up Port F I/O, interrupt, SCL of IIC0 Up Port F I/O, interrupt, SDA of IIC0 Up Port F I/O, interrupt, chip select 3 Freescale Semiconductor ...

Page 59

... KWJ0 RXD2 PK7 EWAIT ROMCTL Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Pin Pin ...

Page 60

... CAN4, RXD of SCI3 CAN4, SCK of SPI0 CAN4, MOSI of SPI0 CAN0 SPI0 CAN0, MISO of SPI0 Disabled Port P I/O, interrupt, channel 7 of PWM/TIM , SCK of SPI2 Disabled Port P I/O, interrupt, channel 6 of PWM/TIM SPI2 Disabled Port P I/O, interrupt, channel 5 of PWM/TIM, MOSI of SPI2 Freescale Semiconductor ...

Page 61

... IOC[5] VREGAPI PT[4:0] IOC[4:0] — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Pin Pin ...

Page 62

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 NOTE Table 1-10 for affected pins. Particular attention is NOTE in all applications. SS Freescale Semiconductor ...

Page 63

... Pierce oscillator/external clock circuitry is used (refer to Configuration). An internal pullup is enabled during reset. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 64

... This will wake up the MCU from stop or wait mode. The XIRQ MC9S12XE-Family Reference Manual , Rev. 1.23 64 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 65

... It can be configured as the transmit pin TXD of serial communication interface 4 (SCI4). Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 66

... CAN4 the serial data pin SDA of the IIC0 module. MC9S12XE-Family Reference Manual , Rev. 1.23 66 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 67

... ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 68

... MC9S12XE-Family Reference Manual , Rev. 1.23 68 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 69

... PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controller 0 (CAN0). Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 70

... MOSI of the serial peripheral interface 1 (SPI1). MC9S12XE-Family Reference Manual , Rev. 1.23 70 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 71

... PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 0 (SCI0). Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 72

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 NOTE pins are connected together internally. SSX is tied to ground DDR Freescale Semiconductor ...

Page 73

... VSS1, VSS2, VSS3 VDDF Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 VSSA1 — Power Supply Pins for ATD and ...

Page 74

... Freescale for import or sale in the United States prior to September 2010 Nominal Description Voltage 1.8 V Provides operating voltage and ground for the phased-locked loop. This allows the 0 V supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Freescale Semiconductor ...

Page 75

... MCU to drive the core, the memories, and the peripherals. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 shows the clock connections from the CRG to all modules ...

Page 76

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 1.4.1 Chip Configuration Summary. 1.4.2 Power Modes. 1.4.3 Freeze Mode. 1.4.4 System States. Table 1-12.) For Freescale Semiconductor ...

Page 77

... Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-12 ...

Page 78

... MC9S12XE-Family Reference Manual , Rev. 1.23 78 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 79

... Supervisor state on completion of each task. This is the default ’state’ following reset and can be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 80

... Reset Source Mask Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None Illegal Address Reset None Clock monitor reset None COP watchdog reset None Local Enable None None None None PLLCTL (CME, SCME) COP rate select Freescale Semiconductor ...

Page 81

... Vector base + $C2 $61 Vector base + $C0 $60 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 CCR ...

Page 82

... OVRIE) CAN3RIER (RXFIE) No CAN3TIER No (TXEIE[2:0]) CAN4RIER (WUPIE) Yes CAN4RIER (CSCIE, No OVRIE) CAN4RIER (RXFIE) No CAN4TIER No (TXEIE[2:0]) PIEP (PIEP7-PIEP0) Yes PWMSDN (PWMIE) No Freescale Semiconductor Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...

Page 83

... Vector base + $52 $29 Vector base + $50 $28 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 CCR ...

Page 84

... TSRC2 (TOF) No PACTL (PAOVI) No PACTL (PAI) No ATD0CTL2 (ACMPIE) Yes ATD1CTL2 (ACMPIE) Yes None No None No — None — — None — in the device electrical RST Freescale Semiconductor WAIT Wake up Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No — — ...

Page 85

... FOPT Register FOPT Register Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 1-15 ...

Page 86

... Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1 Table 1-18. ATD1 External Trigger Sources Connectivity Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1 Table 1-17 Table 1- Freescale Semiconductor ...

Page 87

... On smaller derivatives the S12XEPIM module is a subset of the S12XEP100. The registers of the unavailable ports are unimplemented. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev ...

Page 88

... Freescale for import or sale in the United States prior to September 2010 EXTAL C 1 MCU Crystal or Ceramic Resonator XTAL C 2 Crystal Ceramic Resonator R S =1MΩ specified by crystal vendor B S CMOS-Compatible EXTAL External Oscillator MCU XTAL Not Connected V SSPLL SSPLL Freescale Semiconductor ...

Page 89

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev. 1.23 Chapter 1 Device Overview MC9S12XE-Family ...

Page 90

... Chapter 1 Device Overview MC9S12XE-Family MC9S12XE-Family Reference Manual , Rev. 1.23 90 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 91

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MC9S12XE-Family Reference Manual Rev. 1.23 Chapter 1 Device Overview MC9S12XE-Family ...

Page 92

... Chapter 1 Device Overview MC9S12XE-Family MC9S12XE-Family Reference Manual , Rev. 1.23 92 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Freescale Semiconductor ...

Page 93

... Port AD0 and AD1 associated with two 16-channel ATD modules • Port R associated with 1 standard timer (TIM) module • Port L associated with 4 SCI modules Freescale Semiconductor Table 2-1. Revision History Sections Affected • Corrected reduced drive strength to 1/5 • Separated PE1,0 bit descriptions from other PE GPIO 2.3.19/124 • ...

Page 94

... Open drain for wired-or connections • Interrupt inputs with glitch filtering • Reduced input threshold to support low voltage applications 2.2 External Signal Description This section lists and describes the signals that do connect off-chip. 94 NOTE MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor ...

Page 95

... IVD0 UDS GPIO C PC[7:0] DATA[15:8] GPIO D PD[7:0] DATA[7:0] GPIO Freescale Semiconductor NOTE Table 2-2. Pin Functions and Priorities I/O Description I MODC input during RESET I/O S12X_BDM communication pin O High-order external bus address output (multiplexed with IVIS data) I/O General-purpose I/O O Low-order external bus address output ...

Page 96

... O Extended external bus address output (multiplexed with access master output) I/O General-purpose I/O O Extended external bus address output (multiplexed with instruction pipe status bits) I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.23 Pin Function after Reset Mode 4 dependent Mode 3 dependent Freescale Semiconductor ...

Page 97

... RXD1 GPIO PS1 TXD0 GPIO PS0 RXD0 GPIO Freescale Semiconductor I/O Description I/O Enhanced Capture Timer Channels 7 input/output I/O General-purpose I/O I/O Enhanced Capture Timer Channel 5 input/output O VREG Autonomous Periodical Interrupt output I/O General-purpose I/O I/O Enhanced Capture Timer Channels input/output ...

Page 98

... MSCAN1 receive pin I MSCAN0 receive pin I/O Serial Peripheral Interface 0 master in/slave out pin I/O General-purpose I/O O MSCAN0 transmit pin I/O General-purpose I/O I MSCAN0 receive pin I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.23 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 99

... MOSI1 (TIMIOC1) GPIO/KWP1 PP0 PWM0 MISO1 (TIMIOC0) GPIO/KWP0 Freescale Semiconductor I/O Description I/O Pulse Width Modulator input/output channel 7 I/O Serial Peripheral Interface 2 serial clock pin I/O Timer Channel 7 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 6 I/O Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode ...

Page 100

... I/O Serial Peripheral Interface 1 master out/slave in pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 master in/slave out pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt MC9S12XE-Family Reference Manual , Rev. 1.23 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 101

... PAD[15:0] GPIO AN[15:0] AD1 PAD[31:16] GPIO AN[15:0] R PR[7:0] TIMIOC[7:0] GPIO Freescale Semiconductor I/O Description O MSCAN4 transmit pin O Inter Integrated Circuit 0 serial clock line O MSCAN0 transmit pin I/O General-purpose I/O with interrupt I MSCAN4 receive pin I/O Inter Integrated Circuit 0 serial data line ...

Page 102

... I/O Inter Integrated Circuit 0 serial data line I/O General-purpose I/O O Chip select 3 I/O General-purpose I/O O Chip select 2 I/O General-purpose I/O O Chip select 1 I/O General-purpose I/O O Chip select 0 I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.23 Pin Function after Reset GPIO GPIO Freescale Semiconductor ...

Page 103

... DDRE6 DDRE W 0x000A R 0x000B W Non-PIM Address Range 0x000C R PUPKE BKPUE PUCR W 0x000D R 0 RDPK RDRIV W = Unimplemented or Reserved Freescale Semiconductor 5 4 PA5 PA4 PB5 PB4 DDRA5 DDRA4 DDRA3 DDRB5 DDRB4 DDRB3 PC5 PC4 PD5 PD4 DDRC5 DDRC4 DDRC3 DDRD5 DDRD4 DDRD3 PE5 ...

Page 104

... PTT5 PTT4 PTIT5 PTIT4 PTIT3 DDRT5 DDRT4 DDRT3 RDRT5 RDRT4 RDRT3 MC9S12XE-Family Reference Manual , Rev. 1. EDIV2 EDIV1 PK3 PK2 PK1 DDRK2 DDRK1 PTT3 PTT2 PTT1 PTIT2 PTIT1 DDRT2 DDRT1 RDRT2 RDRT1 Freescale Semiconductor Bit 0 EDIV0 PK0 DDRK0 PTT0 PTIT0 DDRT0 RDRT0 ...

Page 105

... WOMS W 0x024F Reserved W 0x0250 R PTM7 PTM6 PTM W 0x0251 R PTIM7 PTIM6 PTIM W 0x0252 R DDRM7 DDRM6 DDRM W = Unimplemented or Reserved Freescale Semiconductor 5 4 PERT5 PERT4 PERT3 PPST5 PPST4 PPST3 PTS5 PTS4 PTIS5 PTIS4 PTIS3 DDRS5 DDRS4 DDRS3 RDRS5 RDRS4 RDRS3 PERS5 PERS4 PERS3 PPSS5 ...

Page 106

... PTP2 PTP1 PTIP2 PTIP1 DDRP2 DDRP1 RDRP2 RDRP1 PERP2 PERP1 PPSP2 PPSP1 PIEP2 PIEP1 PIFP2 PIFP1 PTH2 PTH1 PTIH2 PTIH1 DDRH2 DDRH1 Freescale Semiconductor Bit 0 RDRM0 PERM0 PPSM0 WOMM0 MODRR0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSP0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 ...

Page 107

... PIEJ7 PIEJ6 PIEJ W 0x026F R PIFJ7 PIFJ6 PIFJ W 0x0270 R PT0AD07 PT0AD06 PT0AD0 W 0x0271 R PT1AD07 PT1AD06 PT1AD0 W = Unimplemented or Reserved Freescale Semiconductor 5 4 RDRH5 RDRH4 RDRH3 PERH5 PERH4 PERH3 PPSH5 PPSH4 PPSH3 PIEH5 PIEH4 PIEH3 PIFH5 PIFH4 PIFH3 PTJ5 PTJ4 PTIJ5 PTIJ4 PTIJ3 DDRJ5 ...

Page 108

... PT0AD15 PT0AD14 PT0AD13 PT1AD15 PT1AD14 PT1AD13 PER0AD15 PER0AD14 PER0AD13 PER1AD15 PER1AD14 PER1AD13 Non-PIM Address Range MC9S12XE-Family Reference Manual , Rev. 1. PER0AD02 PER0AD01 PER0AD00 PER1AD02 PER1AD01 PER1AD00 PT0AD12 PT0AD11 PT1AD12 PT1AD11 PER0AD12 PER0AD1‘ PER0AD10 PER1AD12 PER1AD11 PER1AD10 Freescale Semiconductor Bit 0 PT0AD10 PT1AD10 ...

Page 109

... R PERL7 PERL6 PERL W 0x0375 R PPSL7 PPSL6 PPSL W 0x0376 R WOML7 WOML6 WOML W 0x0377 R PTLRR7 PTLRR6 PTLRR W = Unimplemented or Reserved Freescale Semiconductor 5 4 PTR5 PTR4 PTR3 PTIR5 PTIR4 PTIR3 DDRR5 DDRR4 DDRR3 RDRR5 RDRR4 RDRR3 PERR5 PERR4 PERR3 PPSR5 PPSR4 PPSR3 0 0 PTRRR5 PTRRR4 ...

Page 110

... RDRF4 RDRF3 PERF5 PERF4 PERF3 PPSF5 PPSF4 PPSF3 0 0 PTFRR5 PTFRR4 PTFRR3 MC9S12XE-Family Reference Manual , Rev. 1. PTF3 PTF2 PTF1 PTIF2 PTIF1 DDRF2 DDRF1 RDRF2 RDRF1 PERF2 PERF1 PPSF2 PPSF1 PTFRR2 PTFRR1 Freescale Semiconductor Bit 0 PTF0 PTIF0 DDRF0 RDRF0 PERF0 PPSF0 0 PTFRR0 ...

Page 111

... Always “0” on Port AD0, and AD1. 2. Applicable only on Port P, H, and J. All register bits in this module are completely synchronous to internal clocks during a register read. Freescale Semiconductor Table 2-3. Pin Configuration Summary (1) ( Function x 0 Input 0 0 Input 1 0 Input 0 1 Input ...

Page 112

... Figure 2-2. Port B Data Register (PORTB) MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PA2 PA1 ADDR9 ADDR10 mux mux IVD10 IVD9 Access: User read/write PB2 PB1 ADDR1 ADDR2 mux mux IVD2 IVD1 Freescale Semiconductor (1) 0 PA0 ADDR8 mux IVD8 0 (1) 0 PB0 ADDR0 mux IVD0 or UDS 0 ...

Page 113

... Figure 2-4. Port B Data Direction Register (DDRB) 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Freescale Semiconductor Description 5 4 ...

Page 114

... Table 2-7. DDRB Register Field Descriptions Description 5 4 PC5 PC4 PC3 DATA13 DATA12 DATA11 0 0 Figure 2-5. Port C Data Register (PORTC) Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PC2 PC1 DATA10 DATA9 Freescale Semiconductor (1) 0 PC0 DATA8 0 ...

Page 115

... Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Freescale Semiconductor 5 4 PD5 ...

Page 116

... When operating a pin as a general purpose I/O, the associated data direction bit determines whether input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. 116 Description 5 4 DDRD5 DDRD4 DDRD3 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write DDRD2 DDRD1 Freescale Semiconductor (1) 0 DDRD0 0 ...

Page 117

... Port E general purpose input data and interrupt—Data Register, IRQ input. PE This pin can be used as general purpose and IRQ input. 0 Port E general purpose input data and interrupt—Data Register, XIRQ input. PE This pin can be used as general purpose and XIRQ input. Freescale Semiconductor 5 4 PE5 PE4 PE3 MODA ...

Page 118

... Figure 2-11. S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) 1. Read:Anytime in single-chip modes. Write:Anytime, except BKPUE which is writable in Special Test Mode only. 118 5 4 DDRE5 DDRE4 DDRE3 0 0 Description PUPEE PUPDE 0 1 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write DDRE2 Access: User read/write PUPCE PUPBE Freescale Semiconductor ( (1) 0 PUPAE 0 ...

Page 119

... This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Freescale Semiconductor Description MC9S12XE-Family Reference Manual , Rev. 1.23 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 120

... If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 120 RDPE RDPD 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDPC RDPB Freescale Semiconductor (1) 0 RDPA 0 ...

Page 121

... Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 2. Reset values in emulation modes are identical to those of the target mode. Freescale Semiconductor Description 5 4 ...

Page 122

... ECLK rate = Bus Clock rate divided by 32 2.3.16 PIM Reserved Register Address 0x001D (PRR Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented 122 Description Figure 2-14. PIM Reserved Register MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read Freescale Semiconductor ( ...

Page 123

... This register is reserved for factory testing of the PIM module and is not available in normal operation. Address 0x001F Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented Writing to this register when in special modes can alter the pin functionality. Freescale Semiconductor Figure 2-15. IRQ Control Register (IRQCR) Description Figure 2-16 ...

Page 124

... Figure 2-17. Port K Data Register (PORTK) Description 5 4 DDRK5 DDRK4 DDRK3 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PK2 PK1 ADDR18 ADDR17 mux mux IQSTAT2 IQSTAT1 Access: User read/write DDRK2 DDRK1 Freescale Semiconductor (1) 0 PK0 ADDR16 mux IQSTAT0 0 (1) 0 DDRK0 0 ...

Page 125

... Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Description 5 4 ...

Page 126

... Figure 2-20. Port T Input Register (PTIT) Table 2-21. PTIT Register Field Descriptions Description 5 4 DDRT5 DDRT4 DDRT3 0 0 Table 2-22. DDRT Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIT2 PTIT1 Access: User read/write DDRT2 DDRT1 Freescale Semiconductor (1) 0 PTIT0 u (1) 0 DDRT0 0 ...

Page 127

... PERT These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor NOTE 5 4 RDRT5 RDRT4 ...

Page 128

... PPST4 PPST3 0 0 Table 2-25. PPST Register Field Descriptions Description Figure 2-25. PIM Reserved Register Figure 2-26. PIM Reserved Register MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PPST2 PPST1 Access: User read Access: User read Freescale Semiconductor (1) 0 PPST0 ...

Page 129

... Port S bits 2 is associated with the RXD signal of the SCI1 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTS5 ...

Page 130

... Unaffected by reset Figure 2-28. Port S Input Register (PTIS) Table 2-27. PTIS Register Field Descriptions Description 5 4 DDRS5 DDRS4 DDRS3 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIS2 PTIS1 Access: User read/write DDRS2 DDRS1 Freescale Semiconductor (1) 0 PTIS0 u (1) 0 DDRS0 0 ...

Page 131

... This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the function used on the pins pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. Freescale Semiconductor Description NOTE 5 ...

Page 132

... Table 2-30. PERS Register Field Descriptions Description 5 4 PPSS5 PPSS4 PPSS3 0 0 Table 2-31. PPSS Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PERS2 PERS1 Access: User read/write PPSS2 PPSS1 Freescale Semiconductor (1) 0 PERS0 1 (1) 0 PPSS0 0 ...

Page 133

... Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. 2.3.36 PIM Reserved Register Address 0x024F Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented Freescale Semiconductor 5 4 WOMS5 WOMS4 WOMS3 0 0 Description Unaffected by reset Figure 2-34. PIM Reserved Register MC9S12XE-Family Reference Manual , Rev. 1.23 ...

Page 134

... Figure 2-35. Port M Data Register (PTM) Table 2-33. PTM Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PTM2 PTM1 RXCAN1 TXCAN0 (RXCAN0) — — — — (MISO0) — — — — Freescale Semiconductor (1) 0 PTM0 RXCAN0 — — — — 0 ...

Page 135

... Port M Input Register (PTIM) Address 0x0251 PTIM7 PTIM6 W Reset Unimplemented or Reserved Freescale Semiconductor Description 5 4 PTIM5 PTIM4 PTIM3 Unaffected by reset Figure 2-36. Port M Input Register (PTIM) MC9S12XE-Family Reference Manual , Rev. 1.23 Chapter 2 Port Integration Module (S12XEPIMV1) Access: User read ...

Page 136

... The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. 136 Table 2-34. PTIM Register Field Descriptions Description 5 4 DDRM5 DDRM4 DDRM3 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write DDRM2 DDRM1 Freescale Semiconductor (1) 0 DDRM0 0 ...

Page 137

... Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. Freescale Semiconductor Description NOTE MC9S12XE-Family Reference Manual , Rev. 1.23 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 138

... This bit has no effect if the pin is used as push-pull output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. 138 5 4 RDRM5 RDRM4 RDRM3 0 0 Description 5 4 PERM5 PERM4 PERM3 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDRM2 RDRM1 Access: User read/write PERM2 PERM1 Freescale Semiconductor (1) 0 RDRM0 0 (1) 0 PERM0 0 ...

Page 139

... A logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. Freescale Semiconductor 5 4 PPSM5 PPSM4 ...

Page 140

... MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write MODRR2 MODRR1 Related Pins TXCAN PM1 PM3 PM5 PJ7 PJ7 PM5 PM7 Reserved MOSI SCK SS PS5 PS6 PS7 PM4 PM5 PM3 PP1 PP2 PP3 PH1 PH2 PH3 PP5 PP7 PP6 PH5 PH6 PH7 Freescale Semiconductor (1) 0 MODRR0 0 ...

Page 141

... When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTP5 ...

Page 142

... PTIP7 PTIP6 W Reset Unimplemented or Reserved 1. Read: Anytime. Write:Never, writes to this register have no effect. 142 Description 5 4 PTIP5 PTIP4 PTIP3 Unaffected by reset Figure 2-44. Port P Input Register (PTIP) MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIP2 PTIP1 Freescale Semiconductor (1) 0 PTIP0 u ...

Page 143

... Associated pin is configured as output. 0 Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. Freescale Semiconductor Table 2-42. PTIP Register Field Descriptions Description 5 4 ...

Page 144

... Pull device disabled. 144 5 4 RDRP5 RDRP4 RDRP3 0 0 Description 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-45. PERP Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDRP2 RDRP1 Access: User read/write PPSP2 PPSP1 Freescale Semiconductor (1) 0 RDRP0 0 (1) 0 PPSP0 0 ...

Page 145

... Write: Anytime. Field 7-0 Port P interrupt enable— PIEP This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt flag masked). Freescale Semiconductor 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-46. PPSP Register Field Descriptions ...

Page 146

... PTH3 MOSI2 MISO2 SS1 TXD4 RXD4 TXD7 0 0 Figure 2-51. Port H Data Register (PTH) MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PIFP2 PIFP1 Access: User read/write PTH2 PTH1 SCK1 MOSI1 RXD7 TXD6 Freescale Semiconductor (1) 0 PIFP0 0 (1) 0 PTH0 MISO1 RXD6 0 ...

Page 147

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Table 2-49. PTH Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev ...

Page 148

... Unaffected by reset Figure 2-52. Port H Input Register (PTIH) Table 2-50. PTIH Register Field Descriptions Description 5 4 DDRH5 DDRH4 DDRH3 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIH2 PTIH1 Access: User read/write DDRH2 DDRH1 Freescale Semiconductor (1) 0 PTIH0 u (1) 0 DDRH0 0 ...

Page 149

... In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor Description MC9S12XE-Family Reference Manual , Rev. 1.23 Chapter 2 Port Integration Module (S12XEPIMV1) ...

Page 150

... If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 150 Description NOTE 5 4 RDRH5 RDRH4 RDRH3 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDRH2 RDRH1 Freescale Semiconductor (1) 0 RDRH0 0 ...

Page 151

... Port H pin, if enabled by the associated bit in register PERH and if the port is used as input falling edge on the associated Port H pin sets the associated flag bit in the PIFH register.A pull-up device is connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used as input. Freescale Semiconductor 5 4 PERH5 PERH4 ...

Page 152

... Table 2-55. PPSP Register Field Descriptions Description 5 4 PIFH5 PIFH4 PIFH3 0 0 Table 2-56. PPSP Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PIEH2 PIEH1 Access: User read/write PIFH2 PIFH1 Freescale Semiconductor (1) 0 PIEH0 0 (1) 0 PIFH0 0 ...

Page 153

... This pin is associated with the chip select output signal CS2. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PTJ5 ...

Page 154

... Unaffected by reset Figure 2-60. Port J Input Register (PTIJ) Table 2-58. PTIJ Register Field Descriptions Description 5 4 DDRJ5 DDRJ4 DDRJ3 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIJ2 PTIJ1 Access: User read/write DDRJ2 DDRJ1 Freescale Semiconductor (1) 0 PTIJ0 u (1) 0 DDRJ0 0 ...

Page 155

... The enabled CS1 signal forces the I/O state output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor Table 2-59. DDRJ Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 ...

Page 156

... Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 156 Description NOTE 5 4 RDRJ5 RDRJ4 RDRJ3 0 0 Table 2-60. RDRJ Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDRJ2 RDRJ1 Freescale Semiconductor (1) 0 RDRJ0 0 ...

Page 157

... Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input falling edge on the associated Port J pin sets the associated flag bit in the PIFJ register.A pull-up device is connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. Freescale Semiconductor 5 4 PERJ5 PERJ4 ...

Page 158

... Table 2-63. PPSP Register Field Descriptions Description 5 4 PIFJ5 PIFJ4 PIFJ3 0 0 Table 2-64. PPSP Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PIEJ2 PIEJ1 Access: User read/write PIFJ2 PIFJ1 Freescale Semiconductor (1) 0 PIEJ0 0 (1) 0 PIFJ0 0 ...

Page 159

... When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PT0AD05 ...

Page 160

... Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0) 1. Read: Anytime. Write: Anytime. 160 5 4 DDR0AD05 DDR0AD04 DDR0AD03 0 0 Description NOTE NOTE 5 4 DDR1AD05 DDR1AD04 DDR1AD03 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write DDR0AD02 DDR0AD01 Access: User read/write DDR1AD02 DDR1AD01 Freescale Semiconductor (1) 0 DDR0AD00 0 (1) 0 DDR1AD00 0 ...

Page 161

... This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduced independent of the function used on the pins pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. Freescale Semiconductor Description NOTE NOTE ...

Page 162

... Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. 162 5 4 RDR1AD05 RDR1AD04 RDR1AD03 0 0 Description 5 4 PER0AD05 PER0AD04 PER0AD03 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDR1AD02 RDR1AD01 Access: User read/write PER0AD02 PER0AD01 Freescale Semiconductor (1) 0 RDR1AD00 0 (1) 0 PER0AD00 0 ...

Page 163

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bits of these pins are set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PER1AD05 ...

Page 164

... Associated pin is configured as input. 164 5 4 PT1AD15 PT1AD14 PT1AD13 AN5 AN4 AN3 0 0 Description 5 4 DDR0AD15 DDR0AD14 DDR0AD13 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PT1AD12 PT1AD11 AN2 AN1 Access: User read/write DDR0AD12 DDR0AD11 Freescale Semiconductor (1) 0 PT1AD10 AN0 0 (1) 0 DDR0AD10 0 ...

Page 165

... Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PT0AD1 registers, when changing the DDR1AD1 register. To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”. Freescale Semiconductor NOTE NOTE 5 4 ...

Page 166

... Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. 166 5 4 RDR0AD15 RDR0AD14 RDR0AD13 0 0 Description 5 4 RDR1AD15 RDR1AD14 RDR1AD13 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDR0AD12 RDR0AD11 Access: User read/write RDR1AD12 RDR1AD11 Freescale Semiconductor (1) 0 RDR0AD10 0 (1) 0 RDR1AD10 0 ...

Page 167

... PER1AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor 5 4 PER0AD15 PER0AD14 PER0AD13 ...

Page 168

... PTIR4 PTIR3 Unaffected by reset Figure 2-84. Port R Input Register (PTIR) Table 2-82. PTIR Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PTR2 PTR1 TIMIOC2 TIMIOC1 Access: User read PTIR2 PTIR1 Freescale Semiconductor (1) 0 PTR0 TIMIOC0 0 (1) 0 PTIR0 u ...

Page 169

... PTR or PTIR registers, when changing the DDRR register. 2.3.88 Port R Reduced Drive Register (RDRR) Address 0x036B RDRR7 RDRR6 W Reset 0 0 Figure 2-86. Port R Reduced Drive Register (RDRR) 1. Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 DDRR5 DDRR4 DDRR3 0 0 Description NOTE 5 4 RDRR5 RDRR4 RDRR3 0 0 MC9S12XE-Family Reference Manual , Rev ...

Page 170

... Write: Anytime. 170 Description 5 4 PERR5 PERR4 PERR3 0 0 Table 2-85. PERR Register Field Descriptions Description 5 4 PPSR5 PPSR4 PPSR3 0 0 MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PERR2 PERR1 Access: User read/write PPSR2 PPSR1 Freescale Semiconductor (1) 0 PERR0 0 (1) 0 PPSR0 0 ...

Page 171

... This register configures the re-routing of the associated TIM channel. 1 TIMIOC7 is available on PP7 0 TIMIOC7 is available on PR7 6 Port R routing— PTRRR This register configures the re-routing of the associated TIM channel. 1 TIMIOC6 is available on PP6 0 TIMIOC6 is available on PR6 Freescale Semiconductor Table 2-86. PPSR Register Field Descriptions Description Figure 2-89 ...

Page 172

... Altern. (TXD7) (RXD7) Function Reset Read: Anytime. Write: Anytime. 172 Description 5 4 PTL5 PTL4 PTL3 (TXD6) (RXD6) (TXD5 Figure 2-91. Port L Data Register (PTL) MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PTL2 PTL1 (RXD5) (TXD4 Freescale Semiconductor (1) 0 PTL0 (RXD4) 0 ...

Page 173

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. Freescale Semiconductor Table 2-88. PTL Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev ...

Page 174

... Figure 2-92. Port L Input Register (PTIL) Table 2-89. PTIL Register Field Descriptions Description 5 4 DDRL5 DDRL4 DDRL3 0 0 Table 2-90. DDRL Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read PTIL2 PTIL1 Access: User read/write DDRL2 DDRL1 Freescale Semiconductor (1) 0 PTIL0 u (1) 0 DDRL0 0 ...

Page 175

... These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled. Freescale Semiconductor NOTE 5 4 RDRL5 ...

Page 176

... Output buffers operate as push-pull outputs. 176 5 4 PPSL5 PPSL4 PPSL3 0 0 Table 2-93. PPSL Register Field Descriptions Description 5 4 WOML5 WOML4 WOML3 0 0 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write PPSL2 PPSL1 Access: User read/write WOML2 WOML1 Freescale Semiconductor (1) 0 PPSL0 0 (1) 0 WOML0 0 ...

Page 177

... Module 2.3.101 Port F Data Register (PTF) Address 0x0378 PTF7 PTFT6 W Altern. (TXD3) (RXD3) Function Reset Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 PTLRR5 PTLRR4 0 0 Figure 2-98. Port L Routing Register (PTLRR) Table 2-95. Port L Routing Summary PTLRR Related Pins TXD SCI7 0 ...

Page 178

... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered pin input state is read. 178 Table 2-96. PTF Register Field Descriptions Description MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor ...

Page 179

... SCI transmit channel is enabled forced input if the SCI receive channel is enabled. The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Freescale Semiconductor 5 4 PTIF5 ...

Page 180

... NOTE 5 4 RDRF5 RDRF4 RDRF3 0 0 Table 2-99. RDRF Register Field Descriptions Description 5 4 PERF5 PERF4 PERF3 1 1 Description MC9S12XE-Family Reference Manual , Rev. 1.23 Access: User read/write RDRF2 RDRF1 Access: User read/write PERF2 PERF1 Freescale Semiconductor (1) 0 RDRF0 0 (1) 0 PERF0 1 ...

Page 181

... Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented 2.3.108 Port F Routing Register (PTFRR) Address 0x037F Reset Unimplemented or Reserved Figure 2-106. Port F Routing Register (PTFRR) 1. Read: Anytime. Write: Anytime. Freescale Semiconductor 5 4 PPSF5 PPSF4 PPSF3 0 0 Description Figure 2-105. PIM Reserved Register 5 4 ...

Page 182

... Table 2-102. Port F Routing Summary PTFRR Example 2-1. Selecting a pull-up device MC9S12XE-Family Reference Manual , Rev. 1.23 Related Pins TXD RXD PM7 PM6 PF7 PF6 SCL SDA PJ7 PJ6 PF5 PF4 CS PJ0 PF3 PJ5 PF2 PJ2 PF1 PJ4 PF0 Freescale Semiconductor ...

Page 183

... This is a read-only register and always returns the buffered state of the pin 2.4.2.3 Data direction register (DDRx) This register defines whether the pin is used as an input or an output peripheral module controls the pin the contents of the data direction register is ignored Freescale Semiconductor Table 2-103. Register availability per port Reduced Pull Polarity ...

Page 184

... Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 184 PTI DDR 0 1 data out output enable module enable MC9S12XE-Family Reference Manual , Rev. 1.23 PIN Freescale Semiconductor ...

Page 185

... Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions. Port E pin PE[7] can be used for either general-purpose I the free-running clock ECLKX2 output running at the Core Clock rate. The clock output is always enabled in emulation modes. Freescale Semiconductor NOTE MC9S12XE-Family Reference Manual , Rev. 1.23 ...

Page 186

... Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem. Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem. Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem. 186 MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor ...

Page 187

... Port J pins PJ[7:6] can be used for either general purpose I/O, or with the CAN4, IIC0 or CAN0 subsystems. Port J pins PJ[5:4] can be used for either general purpose I/O, or with the IIC1 subsystem or as chip select outputs. Freescale Semiconductor MC9S12XE-Family Reference Manual , Rev. 1.23 Chapter 2 Port Integration Module (S12XEPIMV1) 187 ...

Page 188

... Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem. Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem. Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects. 188 MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor ...

Page 189

... Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0) Pulse Ignored Uncertain Valid 1. These values include the spread of the oscillator frequency over temper- ature, voltage and process. Freescale Semiconductor (Figure 2-109) shorter than a specified time from generating an uncertain t pign t pval Table 2-104 ...

Page 190

... It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. 190 t pulse Figure 2-109. Pulse Illustration MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor ...

Page 191

... The local address space for each master is translated to a global memory space. MC9S12XE-Family Reference Manual , Rev. 1.23 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 3-1 ...

Page 192

... MC9S12XE-Family Reference Manual , Rev. 1.23 192 Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Table 3-2. Acronyms and Abbreviations Freescale Semiconductor ...

Page 193

... In normal and special single chip mode the internal memory is used. External bus is not active. 1. Resources are also called targets. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 194

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 CPU XGATE Address Decoder & Priority Target Bus Controller EBI RAM Figure 3-1. MMC Block Diagram FLEXRAY DBG Peripherals Freescale Semiconductor ...

Page 195

... O CS2 O CS3 O Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Description Mode input Mode input ...

Page 196

... EP5 EP4 = Unimplemented or Reserved Figure 3-2. MMC Register Summary Figure 3-2. Detailed descriptions Bit 0 CS1E1 CS1E0 CS0E1 CS0E0 GP3 GP2 GP1 GP0 DP11 DP10 DP9 DP8 ROMON PIX3 PIX2 PIX1 PIX0 RP3 RP2 RP1 RP0 EP3 EP2 EP1 EP0 Freescale Semiconductor ...

Page 197

... XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 ...

Page 198

... FLASHSIZE Table 3-16) the CS2 is asserted in the space occupied by this on- Section 3.3.2.5, “MMC Control Register Table 3-7 and Table 3-7 and Table 3-7 and Table 3-7 and Top Address (1) 0x0F_FFFF minus RAMSIZE 0x1F_FFFF 0x3F_FFFF (4) (MMCCTL1)) Freescale Semiconductor ...

Page 199

... Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers ...

Page 200

... Freescale for import or sale in the United States prior to September 2010 RESET 010 Special Test (ST) 010 Normal Expanded 101 (NX) 101 Emulation 101 Expanded (EX) 011 Special Single-Chip (SS) 000 000 RESET 110 Illegal (MODC, MODB, MODA) pin values. 111 Do not use. (Reserved for future use). 101 RESET 011 RESET Freescale Semiconductor ...

Related keywords