MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 1169

• Manufacturer Part Number: MC9S12XEP100MAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, SSI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.3.2.12 EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
29.3.2.13 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
Freescale Semiconductor
Offset Module Base + 0x000C
Offset Module Base + 0x000D
Reset
Reset
W
W
R
R
0
0
7
7
CCOBIX[2:0]
= Unimplemented or Reserved
= Unimplemented or Reserved
011
100
101
Table 29-26. FCCOB - NVM Command Mode (Typical Usage)
Figure 29-19. EEE Tag Counter Low Register (ETAGLO)
Figure 29-18. EEE Tag Counter High Register (ETAGHI)
0
0
6
6
Section
MC9S12XE-Family Reference Manual , Rev. 1.23
Byte
LO
LO
LO
HI
HI
HI
0
0
5
5
29.3.2.4). Once ECC fault information has been stored, no other
FCCOB Parameter Fields (NVM Command Mode)
0
0
4
4
ETAG[15:8]
ETAG[7:0]
Data 1 [15:8]
Data 2 [15:8]
Data 3 [15:8]
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
Data 1 [7:0]
Data 2 [7:0]
Data 3 [7:0]
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0
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