MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 1154

• Manufacturer Part Number: MC9S12XEP100MAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, SSI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
29.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
1154
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
Field
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
7
Figure 29-4. FTM1024K5 Register Summary (continued)
Section 29.4.1, “Flash Command Operations,”
0
6
Figure 29-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
Table 29-9
MC9S12XE-Family Reference Manual , Rev. 1.23
6
Table 29-8. FCLKDIV Field Descriptions
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
5
CAUTION
0
4
Description
4
FDIV[6:0]
0
3
for more information.
3
0
2
2
Freescale Semiconductor
0
1
1
0
0
0