MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 680

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
18.1.4
Figure 18-1
18.2
The PIT module has no external pins.
18.3
This section consists of register descriptions in address order of the PIT. Each description includes a
standard register diagram with an associated figure number. Details of register bit and field function follow
the register diagrams, in bit order.
680
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Bus Clock
Run mode
This is the basic mode of operation.
Wait mode
PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register.
In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates
like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled.
Stop mode
In full stop mode or pseudo stop mode, the PIT module is stalled.
Freeze mode
PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register.
In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the
PITFRZ bit is set, the PIT module is stalled.
External Signal Description
Register Definition
Block Diagram
shows a block diagram of the PIT module.
Micro Timer 0
Micro Timer 1
8-Bit
8-Bit
MC9S12XE-Family Reference Manual , Rev. 1.23
Micro Time
Base 0
Micro
Time
Base 1
Figure 18-1. PIT24B4C Block Diagram
16-Bit Timer 0
16-Bit Timer 1
16-Bit Timer 2
16-Bit Timer 3
Time-Out 0
Time-Out 1
Time-Out 2
Time-Out 3
Interface
Interface
Interface
Interface
Freescale Semiconductor
Interrupt 0
Trigger 0
Interrupt 1
Trigger 1
Interrupt 2
Trigger 2
Interrupt 3
Trigger 3

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