MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 165
![IC MCU 16BIT 1M FLASH 112-LQFP](/photos/12/42/124253/mc9s12xep100mal_sml.jpg)
MC9S12XEP100MAL
Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100MAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEP100MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XEP100MAL
Manufacturer:
FREESCALE
Quantity:
20 000
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1. Read: Anytime.
2.3.80
Freescale Semiconductor
DDR1AD1
Address 0x027B
Write: Anytime.
Field
Reset
7-0
W
R
DDR1AD17
Port AD1 data direction—
This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port AD1 Data Direction Register 1 (DDR1AD1)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR0AD1 register.
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR1AD1 register.
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
DDR1AD16
Figure 2-78. Port AD1 Data Direction Register 1 (DDR1AD1)
0
6
Table 2-76. DDR1AD1 Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDR1AD15
0
5
DDR1AD14
NOTE
NOTE
NOTE
NOTE
0
4
Description
DDR1AD13
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDR1AD12
0
2
DDR1AD11
Access: User read/write
0
1
DDR1AD10
0
0
165
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