MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 179

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC9S12XEP100MAL
0
1. Read: Anytime.
1. Read: Anytime.
2.3.102 Port F Input Register (PTIF)
2.3.103 Port F Data Direction Register (DDRF)
Freescale Semiconductor
Address 0x0379
Address 0x037A
Write:Never, writes to this register have no effect.
Write: Anytime.
DDRF
Field
Field
PTIF
Reset
Reset
7-0
7-0
W
W
R
R
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port F data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRF7
PTIF7
u
0
7
7
= Unimplemented or Reserved
DDRF6
PTIF6
u
0
6
6
Figure 2-101. Port F Data Direction Register (DDRF)
Table 2-98. DDRF Register Field Descriptions
Table 2-97. PTIF Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-100. Port F Input Register (PTIF)
DDRF5
PTIF5
u
0
5
5
DDRF4
PTIF4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRF3
PTIF3
3
u
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRF2
PTIF2
u
0
2
2
Access: User read/write
DDRF1
PTIF1
u
0
1
1
Access: User read
DDRF0
PTIF0
u
0
0
0
179
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