MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 341

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC9S12XEP100MAL
0
CPU12X Information Byte
CXINF Information Byte
This describes the format of the information byte used only when tracing in Detail Mode. When tracing
from the CPU12X in Detail Mode, information is stored to the trace buffer on all cycles except opcode
fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program
counter. In this case the CSZ and CRW bits indicate the type of access being made by the CPU12X, whilst
the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle (no bus acknowledge)
or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode, information is stored to
the trace buffer on all cycles except opcode fetch and free cycles. The CPU12X entry stored on the same
line is a snapshot of the CPU12X program counter. In this case the XSZ and XRW bits indicate the type
of access being made by the XGATE, whilst the CFREE and COCF bits indicate if the simultaneous
CPU12X cycle is a free cycle or opcode fetch cycle.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
CFREE
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
CSD
CDV
CVA
7
6
4
7
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses
are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal
and Loop1 mode tracing. This bit has no meaning in Pure PC mode.
0 Indexed jump destination address
1 Vector destination address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
CPU12X Free Cycle Indicator — This bit indicates if the stored CPU12X address corresponds to a free cycle.
This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
CFREE
CSD
Bit 7
Bit 7
Bit 6
CVA
Bit 6
CSZ
Figure 8-25. CPU12X Information Byte CINF
MC9S12XE-Family Reference Manual Rev. 1.23
Table 8-46. CXINF Field Descriptions
Figure 8-26. Information Byte CXINF
Table 8-45. CINF Field Descriptions
CRW
Bit 5
Bit 5
0
COCF
Bit 4
CDV
Bit 4
Description
Description
XACK
Bit 3
Bit 3
0
Bit 2
Bit 2
XSZ
0
Chapter 8 S12X Debug (S12XDBGV3) Module
XRW
Bit 1
Bit 1
0
XOCF
Bit 0
Bit 0
0
341

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