MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 769

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
1. n is used later in this document as a placeholder for the selected transfer width.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
MODFEN
SPISWAI
BIDIROE
XFRW
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
SPC0
Field
6
4
3
1
0
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)
1 16-bit Transfer Width (n = 16)
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
Bidirectional
Bidirectional
Pin Mode
Normal
Normal
SPC0
0
1
0
1
Table 21-5. Bidirectional Pin Configurations
Table
MC9S12XE-Family Reference Manual Rev. 1.23
Table 21-4. SPICR2 Field Descriptions
BIDIROE
21-3. In master mode, a change of this bit will abort a transmission in progress and
(1)
X
X
0
1
0
1
1
Master Mode of Operation
Slave Mode of Operation
MISO not used by SPI
Slave Out
Master In
Slave I/O
Description
Slave In
MISO
Section 21.3.2.4, “SPI Status Register (SPISR)
Chapter 21 Serial Peripheral Interface (S12SPIV5)
MOSI not used by SPI
Master Out
Master I/O
Master In
Slave In
MOSI
Table
21-5. In master
for
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