MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 143

• Manufacturer Part Number: MC9S12XEP100MAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, SSI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
2.3.47
Freescale Semiconductor
Address 0x025A
Write: Anytime.
DDRP
DDRP
Field
Field
PTIP
Reset
7-0
6-0
7
W
R
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port P data direction—
This register controls the data direction of pin 7.
The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin
is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this
case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRP7
Port P Data Direction Register (DDRP)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
DDRP6
0
6
Figure 2-45. Port P Data Direction Register (DDRP)
Table 2-43. DDRP Register Field Descriptions
Table 2-42. PTIP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDRP5
0
5
DDRP4
NOTE
0
4
Description
Description
DDRP3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRP2
0
2
Access: User read/write
DDRP1
0
1
DDRP0
0
0
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