MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 231
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MC9S12XEP100MAL
Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100MAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEP100MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XEP100MAL
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 4
Memory Protection Unit (S12XMPUV1)
4.1
The MPU module provides basic functionality required to protect memory mapped resources from
undesired accesses. Multiple address range comparators compare memory accesses against eight memory
protection descriptors located in the MPU module to determine if each access is valid or not. The
comparison is sensitive to which bus master generates the access and the type of the access.
The MPU module can be used to isolate memory ranges accessible by different bus masters. It can be also
be used by an operating system or software kernel to isolate the regions of memory “legally” available to
specific software tasks, with the kernel re-configuring the task specific memory protection descriptors in
supervisor state during task-switching.
4.1.1
The following terms and abbreviations are used in the document.
4.1.2
The MPU module monitors the bus activity of each bus master. The data describing each access is fed into
multiple address range comparators. The output of the comparators is used to determine if a particular
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.04
V01.05
V01.06
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Introduction
supervisor state
Revision Date
14 Sep 2005
Preface
Overview
14 Mar 2006
09 Oct 2006
user state
XGATE
Term
MCU
MPU
CPU
4.3.1.1/4-235
4.3.1.1/4-235
4.4.1/4-241
Micro-Controller Unit
Memory Protection Unit
S12X Central Processing Unit (see S12XCPU Reference Manual)
XGATE Co-processor (see XGATE chapter)
refers to the supervisor state of the S12XCPU (see S12XCPU Reference Manual)
refers to the user state of the S12XCPU (see S12XCPU Reference Manual)
Sections
4.4/4-241
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 4-1. Revision History
- Added note to only use the CPU to clear the AE flag.
- Added disclaimer to avoid changing descriptors while they are in use
because of other bus-masters doing accesses.
- Clarified that interrupt generation is independent of AEF bit state.
- Corrected preliminary statement about execution of violating accesses.
- Made Revision History entries public.
Table 4-2. Terminology
Meaning
Description of Changes
231
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