MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 576

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100MAL

Manufacturer Part Number
MC9S12XEP100MAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
SPI, SSI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.1.1.3
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is
explained in the diagram and notes below.
In
576
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Figure 14-74
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
2. IC Queue Mode (LATQ = 0)
1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.
2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
This will prevent the captured value from being overwritten until it is read or latched in the holding
register.
The main timer value is memorized in the IC register by a valid input pin transition (see
69
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the value of the IC register will be transferred to its holding register and the IC register
memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
if the TFMOD bit of the ICSYS register is set,the timer flags C3F--C0F in TFLG register are set
only when a latch on the corresponding holding register occurs,after C3F--C0F are set,user should
clear flag C3F--C0F,then read TCx and TCxH to make TCx and TCxH be empty.
In queue mode, reads of the holding register will latch the corresponding pulse accumulator value
to its holding register.
accepted, depending on their relative alignment with the sample points.
and
BUS CLOCK
Figure
Delayed IC Channels
INPUT ON
INPUT ON
INPUT ON
INPUT ON
DLY_CNT
a delay counter value of 256 bus cycles is considered.
CH0–3
CH0–3
CH0–3
CH0–3
Figure 14-74. Channel Input Validity with Delay Counter Feature
14-70).
0
MC9S12XE-Family Reference Manual Rev. 1.23
1
2
255.5 Cycles
255.5 Cycles
255 Cycles
256 Cycles
3
253
254
255
Section 14.4.1.1, “IC
Section 14.4.1.1, “IC
256
Accepted
Rejected
Rejected
Accepted
Freescale Semiconductor
Channels”).
Channels”).
Figure 14-

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