MC9S12XEP100MAL Freescale Semiconductor, MC9S12XEP100MAL Datasheet - Page 149

• Manufacturer Part Number: MC9S12XEP100MAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, SSI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
Freescale Semiconductor
Write: Anytime.
DDRH
DDRH
DDRH
DDRH
DDRH
DDRH
Field
7
6
5
4
3
2
Port H data direction—
This register controls the data direction of pin 7.
The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 6.
The enabled SCI5 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 5.
The enabled SCI4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 4.
The enabled SCI4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 3.
The enabled SCI7 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 2.
The enabled SCI7 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Table 2-51. DDRH Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
149