PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 109

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

CONFCC[6:0] (Addr.: 0BH) Configuration of Clock Control unit, write protected,
Reset value = 00H
INVCTRL32
SYNCACT
SYNCODUR
SSCLKEDGE
DISCTRL32
DISSCLKO
DISCLK4O
FSLIPIV[6:0] (Addr.: 0CH) Frame slip safety interval, write protected,
Reset value = 28H
RFCLKEX
RFN
Data Sheet
-
-
CTRL32
CLKEX
INV
RF
'1': SYNCO duration is 2 SCLK periods
'1': Inverts the control voltage signal for the 32MHz VCO at pin
'0': no inversion of the control voltage signal for the 32MHz VCO at
'1': SYNCI/SYNCO is active high (active edge is the rising edge)
'0': SYNCI/SYNCO is active low (active edge is the falling edge)
'0': SYNCO duration is 1 SCLK period
'1': SYNCI is sampled with the rising edge of SCLKI, SYNCO is
'0': SYNCI is sampled with the falling edge of SCLKI, SYNCO is
'1': disables (constantly set to '1') the output of the control voltage
'0': enables the output of the control voltage signal for the 32MHz
'1': disables (constantly set to '1') the output of the system clock at
'0': enables the output of the system clock at pin SCLKO
'1': disables (constantly set to '1') the output of the clock at pin
'0': enables the output of the clock at pin CLK4O
'1': Selects RFCLKEX as reference clock for the 16MHz PLL
'0': Selects RFCLKN or RFCLKF (depending on bit RFN )as
'1': Selects RFCLKN as reference clock for the 16MHz PLL if bit
'0': Selects RFLCKF as reference clock for the 16MHz PLL if bit
CTRL32 (see
pin CTRL32 (see
output with the falling edge of SCLKI (see
output with the rising edge of SCLKI (see
signal for the 32MHz VCO at pin CTRL32
VCO at pin CTRL32
pin SCLKO
CLK4O
reference clock for the 16MHz PLL
RFCLKEX = '0', and RFSPN as external data buffer sync pulse
RFCLKEX = '0', and RFSPF as external data buffer sync pulse
SYNC
RFN
ACT
SYNCO
FSLIP
DUR
IV[4]
Figure
Figure
109
23)
SSCLK
EDGE
FSLIP
IV[3]
23)
CTRL32
FSLIP
IV[2]
DIS
Figure
Register Description
Figure
SCLKO
FSLIP
IV[1]
DIS
Rev. 2, 2004-07-28
21).
21).
PEB 20954
PEF 20954
CLK4O
FSLIP
IV[0]
DIS