PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 23

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Table 3
Pin No. Symbol
131
118
120
129
101
100
Data Sheet
SYNCI
SYNCO
SDECO
SDECI
RFCLKF
RFCLKN
Synchronization (cont’d)
I/O, PU/PD Function
I, PU
O
O
I, PU
I, PU
I, PU
System Synchronization input pulse. Defines
the frame alignment of PCM and UCCI signals
in conjunction with the values in registers
RIALIGN, SIALIGN, SOALIGN, UCCALIGN,
PHALIGN and also the multiframe alignment of
the UCCI. Must be integer multiple of 125 s if
UCC Interface is not used. Must be multiple
integer of 4 ms if UCC interface is used.
Leave open if not used or connect to V
System Synchronization output pulse (see
SYNCI), duration configurable one or two
SCLKO periods, period 125 s. If the UCC
interface is not used and no SYNCI is applied,
SYNCO can take over the part and role of
SYNCI.
Synchronization output pulse for other SIDECs
if this SIDEC uses its own 32.768 MHz VCO.
Can also be used for synchronization of
external devices to the serial control input and
monitor output signals of the SIDEC.The pulse
width is 488 ns with a period of 125 s.
Synchronization input pulse if the SIDEC uses
the 32.768 MHz VCO of another SIDEC. The
same SCLKI signal can be applied to SDECI
and SCLKI pin if the SCLKI is supplied by a
source with correct phase condition to the
CLK32 (see
leave it open or connect it to V
Reference clock (2.048 MHz) for frequency
comparison to generate the control voltage for
the 16.384 MHz VCXO if Register
FSLIPIV[6:5]="00"
Reference clock (2.048 MHz) for frequency
comparison to generate the control voltage for
the 16.384 MHz VCXO if Register
FSLIPIV[6:5]="01"
23
Figure
15). If the pin is not used
Rev. 2, 2004-07-28
Pin Description
DD
.
PEB 20954
PEF 20954
DD