PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 45

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Offset adjustment is implemented at the output of the canceller. The attenuation of 0 dB,
2.5 dB or 6 dB is programmable by a register. The use of this feature requires that the
cancelling function for the corresponding timeslot is enabled.
The complete bypassing of individual timeslots and connections from and to the
processor interface with the internal canceller is provided for testing of cancelling
timeslots.
The least significant bit in the send path can be transmitted transparently to the output if
the corresponding external pin TSIGM is activated (CAS bit robbing).
The block PCM Input/Output Interface provides time multiplexing/demultiplexing for 16
or 32 timeslots. (depending on configuration, see section above). In 128 ms echo end
path mode the selection of timeslots at the input is assigned as follows:
•
•
The PCM Input/Output Interfaces are connected to the Speech Control Unit, Disabling
Logic and the Microprocessor Interface.
3.1.5
The subtractor calculates the difference between the signal from the PCM Send In
Interface and the artificial echo provided by the Adaptive Echo Estimation Unit. The
subtractor is controlled by the Speech Control.
3.1.6
The Non Linear Processor (NLP) limits the residual echo if only far end talk is present.
Three programmable functions are available:
• Block echo and background noise.
• Replace echo and background noise by comfort noise with the level of the determined
• Clip the level of the echo and the background noise to the level of the background
The NLP is controlled by the Disabling Logic and Speech Control.
3.1.7
The Microprocessor Interface can operate in Intel and Motorola Mode. It provides access
to the internal configuration, control states and monitor registers.
3.1.8
The UCC Interface is a serial hardware interface for SIDEC control and supervision by
other boards via a Microprocessor. A special feature of the SIDEC-UCC Interface is, that
Data Sheet
background noise.
noise. (Experiments show that most people prefer this configuration)
Master: Timeslot0,1,2,3, 8,9,10,11,16,17,18,19,
Slave: Timeslot4,5,6,7, 12,13,14,15,20,21,22,23, 28,29,30,31
Subtractor
Non Linear Processor
Microprocessor Interface
Universal Control and Communication Interface
45
24,25,26,27
Functional Description
Rev. 2, 2004-07-28
PEB 20954
PEF 20954