PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 64

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

PEB 20954
PEF 20954
Operational Description
and UCCMFR. For finer adjustments, the valid bit phase of the UCC signals at the first
detection of an active SYNCI with the falling edge of SCLKI can be configured by writing
to the two MSBs of register PHALIGN.
The configured frame and bit phase alignment always denotes the beginning of the ideal
bit phase (no signal delay) at the falling edge of SCLKI. If SYNCI is sampled with the
falling edge of SCLKI (CONFCC.SSCLKEDGE='0') this edge is the synchronization
point for PCM and UCC signals. If SYNCI is sampled with the rising edge of SCLKI
(CONFCC.SSCLKEDGE='1') the next falling SCLKI edge is the synchronization point for
PCM and UCC signals. This behavior is identical to the PCM signal behavior and
illustrated in
Figure 21
in
Chapter 4.2.1
UCC inputs are always sampled with the falling edge of SCLKI at the beginning of bit
phase 2, UCCO and TUCCO are clocked out with the falling edge of SCLKI at the
beginning of bit phase 0. The value of register UCCMFR denotes the frame number of
the next complete frame that starts with phase 0, bit 7, channel 0 after the first detection
of an active SYNCI with the falling edge of SCLKI (see figure below).
Data Sheet
64
Rev. 2, 2004-07-28