PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 96

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Note: In 128 ms mode the DIS-Bit and the FX-Bit are only evaluated in the 16 processed
channels.
UCCMFR[4:0] (Addr.: 61H): UCC Multiframe Alignment, write protected,
Reset value = 00H
UCCMFR[4:0]
UCCFRS[6:0] (Addr.: 62H): Selection of the special UCC Frame FRS,
write protected, Reset value = 00H
NOFRS
128FRSEN
Data Sheet
-
-
NOFRS
-
'0': normal operation
Denotes the UCC frame number for the next complete UCC frame
(beginning with bit 7, phase 0, channel 0) after the first detection of
an active SYNCI impulse with the falling edge of SCLKI (UCC frame
alignment is configured by register UCCALIGN). For explanation
see also
'1': The UCC frame corresponding to the value in UCCFRS[4:0] is not
'0': The UCC frame corresponding to the value in UCCFRS[4:0] is
'1': enables the output of all frames at UCCO and the activation of
the performance of the software and is unpredictable!
handled as the special UCC frame containing global SIDEC
information but as a frame that contains channel individual
information (like the other UCC frames)
handled as the special UCC frame that contains global SIDEC
related (not channel individual) information.
Note: If this setting is configured, the PCM channel that
corresponds to the value in UCCFRS[4:0] can not individually be
controlled directly via UCC and is considered as a PCM channel
containing no payload data. The DIS-Bit and the FX-Bit are not
evaluated for this channel and set inactive. It is the responsibility
of the software to disable the Echo Canceller and Law conversion
function via the channel individual control registers CHCTR* in
order to enable the transparent (64-clear) mode for this channel.
TUCCO for all frames in 128 ms mode even if the number
does not correspond to one of the 16 processed channels.*
128FRS
EN
-
Figure 25
MFR[4]
FRS[4]
UCC
UCC
and
96
Figure
MFR[3]
FRS[3]
UCC
UCC
26.
MFR[2]
FRS[2]
UCC
UCC
Register Description
MFR[1]
FRS[1]
UCC
UCC
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
MFR[0]
FRS[0]
UCC
UCC