PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 139

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PEF 20954 HT V1.1

Manufacturer Part Number
PEF 20954 HT V1.1
Description
IC ECHO CANCELLER DGTL TQFP144
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20954 HT V1.1

Function
Smart Integrated Digital Echo Canceller (SIDEC)
Interface
PCM, Serial, UCC
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
350mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Double Talk Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF20954HTV1.1
SP000007505
6.6.4
Figure 35
In case a 32.768 MHz clock has to be generated and synchronized to the system clock
at SCLKI, the signal at pin CTRL32 can be used to control an external VCO. The output
at CTRL32 is the signal at SCLKI that is internally 'xored' with an internal 8.192 MHz
clock that is derived from the signal pin CLK32 by division by 4. For proper operation of
the SIDEC the system clock SCLKI and the internal 8.192 MHz clock must lock in within
the capture range from 0 to 180 . CTRL32 can be inverted by bit CONFCC.INVCTRL32
for use of VCOs that increase the frequency with falling voltage.
The internal 8.192 MHz clock can be monitored at pin SCLKO with a delay of three
CLK32 periods plus internal signal delay if pin CLK32SEL is set to logic '1'.
Data Sheet
Lock-in at 180°
Lock-in at 90°
Lock-in at 0°
internal 8Mhz clock
internal 8Mhz clock
internal 8Mhz clock
CTRL32
CTRL32
CTRL32
CLK32
CLK32
CLK32
SCLKI
Clock Timing within External VCO Capture Range
Clock Timing within External VCO Capture Range
139
Clock Timing within External VCO Capture Range
Electrical Characteristics
Rev. 2, 2004-07-28
PEB 20954
PEF 20954

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