PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 57

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PEF 20954 HT V1.1

Manufacturer Part Number
PEF 20954 HT V1.1
Description
IC ECHO CANCELLER DGTL TQFP144
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20954 HT V1.1

Function
Smart Integrated Digital Echo Canceller (SIDEC)
Interface
PCM, Serial, UCC
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
350mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Double Talk Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF20954HTV1.1
SP000007505
Figure 18
In multiple SIDEC mode the output SDECO of the clock master SIDEC is used to
synchronize clock slave SIDECs to the system clock. In this application multiple E1/T1
lines can be echo cancelled, one E1/T1 line per SIDEC. Leave the SDECI of the master
SIDEC open or connect it to ground V
4.2.1
The SIDEC requires the MSB (bit7) first and the LSB (bit0) last as input.
Data Sheet
PCM Signal Timing and Frame Alignment
Multiple SIDEC
V
DD
SCLKI
SI
RO
SDECI
SCLKI
RO
SI
SDECI
VCO
SIDEC
SIDEC
DD
master
slave
.
57
SDECO
SO
RI
SDECO
SO
RI
Operational Description
Multiple SIDEC Mode
Rev. 2, 2004-07-28
PEB 20954
PEF 20954

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