PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 22

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

2.2
Table 2
Pin No. Symbol
114
112
113
112
113
Table 3
Pin No. Symbol
111
126
123
130
119
117
Data Sheet
PORES
MODE1
MODE0
MODE1
MODE0
CTRL32
SCLKI
SCLKO
CLK4O
CLK32SEL
CLK32
Pin Definitions and Functions for the P-TQFP-144-8 package
General Pins
Synchronization
Input (I)
Output (O)
Pull Up /
Pull Down
I, PU
I, PU
I, PU
I, PU
I, PU
I/O, PU/PD Function
I, PU
I, PU
O
I, PU
O
O
Function
Power On Reset. A low on this pin forces all
registers and counters to predefined values
1
1
0
1
Selects from which source SCLKO will be
derived:
'1': SCLKO will be derived from CLK32 by
dividing by 4
'0': SCLKO will be derived from CLK16 by
dividing by 2
32.768 MHz Operating Clock for the SIDEC
Control voltage for the 32.768 MHz operating
Clock VCO, maskable for reduced power
consumption
System clock input (8.192 MHz) for PCM- and
UCCI
8.192 MHz system clock output, source CLK32
or CLK16 is selectable via pin CLK32SEL,
maskable for reduced power consumption
4.096 MHz system clock output for subsequent
circuits, derived from SCLKI, maskable for
reduced power consumption
22
End delay <
64ms
End delay <
128 ms Master
Mode
1
0
0
0
Rev. 2, 2004-07-28
Pin Description
For future use
End delay <
128 ms Slave
Mode
PEB 20954
PEF 20954