PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 142
PEF 20954 HT V1.1
Manufacturer Part Number
PEF 20954 HT V1.1
Description
IC ECHO CANCELLER DGTL TQFP144
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20954_HT_V1.1.pdf
(164 pages)
Specifications of PEF 20954 HT V1.1
Function
Smart Integrated Digital Echo Canceller (SIDEC)
Interface
PCM, Serial, UCC
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
350mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Double Talk Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF20954HTV1.1
SP000007505
SP000007505
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6.6.6
Figure 37
Note: Above values are examples only. For the use of the UCC Interface a SYNCI signal
with a period of 4 ms (equivalent to one multiframe) must be applied to the SIDEC. UCC
frame and multiframe alignment with respect to the first detection of an active SYNCI
with the falling edge of SCLKI can be configured by writing to the registers UCCALIGN
Data Sheet
(SYNCO)
(SYNCO)
(SYNCO)
TUCCO
TUCCO
TUCCO
SYNCI
SYNCI
SYNCI
SCLKI
UCCO
SCLKI
UCCO
SCLKI
UCCO
UCCI
UCCI
UCCI
UCC Interface Signal Timing and Frame Alignment
30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12
30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12
channel 31, frame 3
channel 31, frame 3
Bit 2
UCC Interface Signal Timing and Frame Alignment
Bit 0
Bit 0
Bit 1
sampling of UCCI at the
beginning of phase 2
Phase 0
Phase 0
Bit 0
Phase 1
Phase 1
Bit 7
Bit 7
Phase 2
Phase 2
Bit 6
Bit 6
UCC Interface Signal Timing and Frame Alignment
Phase 3
Phase 3
142
Bit 5
Bit 5
4 ms
Register UCCMFR = 05H (next frame = frame 5)
Phase 0
channel 0, frame 4
channel 0, frame 4
Bit 4
Bit 4
Register UCCALIGN = 01H,
Register PHALIGN[7:6] = "00"
Phase 1
Bit 3
Bit 3
Phase 2
Bit 6
Bit 2
Bit 2
Electrical Characteristics
Phase 3
Bit 1
Bit 1
Rev. 2, 2004-07-28
Bit 0
Bit 0
PEB 20954
PEF 20954
Bit 5
Bit 5
Bit 7
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