PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 37

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Table 20
Ball No. Symbol
H14
H13
Table 21
Ball No. Symbol
B6
Data Sheet
SO128
RO128
UCCI
Speech Highways
UCC Interface
I/O, PU/PD Function
I/O, PU/PD Function
I/O, PU
I/O, PU
I, PD
2.048 Mbit/s UCC highway input. Start of
timeslot 0, bit 7 and frame number can be
flexibly aligned to the SYNCI/SYNCO pulse in
122 ns steps via registers UCCMFR,
UCCALIGN and PHALIGN[7:6]
Auxiliary 2.048 Mbit/s Send speech highway
output in 128 ms mode. Input in master mode,
output in slave mode. The pins of master and
slave SIDEC in 128 ms mode should be
connected to enable a 32 channel system. The
signal from the slave is multiplexed in the
master with the internally generated signal and
output (clocked) with the system clock. Tristate
and meaningless in 64 ms mode
Auxiliary 2.048 Mbit/s Receive speech
highway output in 128 ms mode. Input in
master mode, output in slave mode. The pins
of master and slave SIDEC in 128 ms mode
should be connected to enable a 32 channel
system. The signal from the slave is
multiplexed in the master with the internally
generated signal and output (clocked) with the
system clock. Tristate and meaningless in 64
ms mode
37
Rev. 2, 2004-07-28
Pin Description
PEB 20954
PEF 20954