PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 59

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

registers RIALIGN, SIALIGN an SOALIGN. For finer adjustments, the valid bit phase of
the PCM signals at the first detection of an active SYNCI with the falling edge of SCLKI
can be configured by writing to the register PHALIGN. The configured frame and bit
phase alignment always denotes the beginning of the ideal bit phase (no signal delay) at
the falling edge of SCLKI.
PCM inputs are always sampled with the falling edge of SCLKI at the beginning of bit
phase 2, outputs are clocked with the falling edge of SCLKI at the beginning of bit phase
0. Unless not bypased the PCM output RO has a fixed delay of one PCM frame (125 s)
with respect to RI.
.
Figure 20
Figure 21
low active SYNCI signal with respect to the internal 8192 kHz SCLKI signal. If SYNCI is
sampled with the falling edge of SCLKI (CONFCC.SSCLKEDGE='0') this edge is the
synchronization point for PCM and UCC signals. If SYNCI is sampled with the rising
edge of SCLKI (CONFCC.SSCLKEDGE='1') the next falling SCLKI edge is the
synchronization point for PCM and UCC signals. The SYNCO signal may only be used
instead of the SYNCI signal if the UCC Interface is not used
.
Figure 21
Data Sheet
(SYNCO is only possible if
TMFBI
UCC interface is not used)
RO
SO
RI
SI
Bit 6
illustrates the synchronization of the 2048 kBit/s PCM and UCC signal for a
Bit 6
Bit 7
SYNCI
SCLKI
Delay of PCM Signals
PCM and UCC Signal synhcronization to SCLKI and SYNCI
Bit 7
4
Synchronization for UCC Interface
if CONFCC.SSCLKEDGE='0'
5
and PCM Signal
Bit 5
Bit 6
Bit 5
6
Bit 6
59
Synchronization for UCC Interface
if CONFCC.SSCLKEDGE='1'
and PCM Signal
Synchronization of PCM and UCC Signal
Bit 4
CONFCC.SYNCACT = '0' (low active)
Bit 5
Bit 4
Operational Description
Bit 5
Bit 5
Rev. 2, 2004-07-28
Delay of PCM Signals
7
PEB 20954
PEF 20954
Bit 3
Bit 4
Bit 4