PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 111

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

UCCALIGN[7:0] (Addr.: 10H): UCC frame alignment,write protected, Reset value = 00H
UCCALIGN[7:0]
PHALIGN[7:0] (Addr. 11H): Bit Phase alignment for RI, SI, SO and UCC, write
protected, Reset value = 00H,
UCCPHALIGN[1:0]Determines the valid bit phase of the UCC frame bit (starting with
SOPHALIGN[1:0] Determines the valid bit phase of the send output frame bit (starting
SIPHALIGN[1:0]
RIPHALIGN[1:0]
ASTOC[7:0] (Addr.:70H): AFI Saw-Tooth and Offset Characteristic, write protected,
Reset value = 00H
Low frequency components are superimposed to the Receive In AFI input signal to
increase stability. Under normalconditions this superimposition is not necessary.
STRISE[2:0]
Data Sheet
ALIGN[7]
ALIGN[1]
UCCPH
RISE[2]
UCC
ST
ALIGN[6]
ALIGN[0]
UCCPH
RISE[1]
UCC
ST
Determines the valid frame bit of the UCC frame (starting with bit 7
channel 0) at the first falling SCLKI edge, with which an active SYNCI
impulse is detected. (00H = bit 7, channel 0; FFH = bit 0, channel
31). For explanation see
phase 0) at the first falling SCLKI edge, with which an active SYNCI
impulse is detected. ("00" = bit phase 0, "11" = bit phase 3)
For explanation see
with phase 0) at the first falling SCLKI edge, with which an active
SYNCI impulse is detected. ("00" = bit phase 0, "11" = bit phase 3)
For explanation see
Determines the valid bit phase of the send input frame bit (starting
with phase 0) at the first falling SCLKI edge, with which an active
SYNCI impulse is detected. ("00" = bit phase 0, "11" = bit phase 3)
For explanation see
Determines the valid bit phase of the receive input frame bit (starting
with phase 0) at the first falling SCLKI edge, with which an active
SYNCI impulse is detected. ("00" = bit phase 0, "11" = bit phase 3)
For explanation see
Saw-tooth rising clock frequency
ALIGN[5]
ALIGN[1]
RISE[0]
SOPH
UCC
ST
ALIGN[4]
ALIGN[0]
FALL[2]
SOPH
UCC
ST
Figure
Figure
Figure
Figure
111
Figure
ALIGN[3]
ALIGN[1]
FALL[1]
SIPH
UCC
25.
19.
19.
19.
ST
25.
ALIGN[2]
ALIGN[0]
FALL[0]
SIPH
UCC
ST
Register Description
ALIGN[1]
ALIGN[1]
AMPL[1] AMPL[0]
RIPH
UCC
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
ALIGN[0]
ALIGN[0]
RIPH
UCC