PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 25

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Table 4
Pin No. Symbol
67
69
68
64
61
Table 5
Pin No. Symbol
27
28
29
30
Data Sheet
ALE
RD/DS
WR/RW
INT
RDY
UPIO0
UPIO1
UPIO2
UPIO3
Microprocessor Interface (cont’d)
Microcontroller Port Extension
I/O, PU/PD Function
I/O, PU/PD Function
I, PU
I, PU
I, PU
O, (od)
O, (od)
I/O, PU
I/O, PU
I/O, PU
I/O, PU
Address Latch Enable in multiplexed mode.
Address on AD bus is internally latched with
the falling edge of ALE.This signal is also used
for the internal clock supervision.
In Demuxed mode there must be provided an
external independent clock signal (i.e.
processor clock) in order to enable proper
clock supervision.
Intel mode. A low indicates a read operation.
Motorola mode. Data Strobe, active low to
control read/write
Intel mode. A low indicates a write operation.
Motorola mode. High = read cycle,
low = write cycle
Interrupt request from the SIDEC, active low
Ready signal for C devices that support this
feature. For read cycles the signal is asserted
after the data on the AD bus is valid. For writing
cycles the signal is asserted when a write
access is ready to be concluded.
Pin that can be read and controlled by the on
board processor via register UPIO
Pin that can be read and controlled by the on
board processor via register UPIO
Pin that can be read and controlled by the on
board processor via register UPIO
Pin that can be read and controlled by the on
board processor via register UPIO
25
Rev. 2, 2004-07-28
Pin Description
PEB 20954
PEF 20954