PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 44

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

(described in Section
necessary. The H-Register reset signal is also provided by the Speech Control.
3.1.2
Upon request of the Speech Control and depending on external inputs the Disabling
Logic disables the Non Linear Processor and/or the Subtractor or even the complete
Echo Canceller.
If the Speech Control Unit detects, that one of the following conditions is applied to the
Echo Canceller, it will disable the device via the Disabling Logic:
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3.1.3
The Adaptive Echo Estimation Unit contains for each 8 bit signal sampled at 8 kHz
memory for 512 / 1024 byte. This is equivalent to 64 / 128 ms end echo path delay.
Depending on the end echo path delay of 64 or 128 ms the Adaptive Echo Estimation
Unit processes 32 or 16 channels simultaneously, respectively. The corresponding 32 /
16 H-Register for each channel representing the pulse response of the complete echo
path are also stored in the Adaptive Echo Estimation Unit. This information simplifies the
detection of double speech. A highly sophisticated and patented algorithm guarantees
fast and stable convergence even in the presence of near end speech.
The Adaptive Echo Estimation Unit is connected to the Microprocessor Interface in order
to configure parameters of the algorithm and to read the content of the H-Register.
3.1.4
Each PCM Input/Output Interface contains a delay element, that is adjustable for max
125 s delay in 122 ns steps in order to align the corresponding PCM signal to the
synchronizing pulse. Unless not bypassed, the delay from Receive In to Receive Out is
fixed to one PCM Frame equivalent to 125 s. The signal Multiframe Begin is delayed
accordingly to the send path delay.
Encoder to convert A- or -Law PCM signals to linear, and decoder to convert linear PCM
signals to A- or -Law allow for channelwise Law Conversion (transcoding).
Data Sheet
Disabling via 2100 Hz tone without phase reversal
Disabling via 2100 Hz tone with phase reversal
Disabling via 2010 Hz continuity check
Disabling via PCM timeslot 16 Bit a, b, c or d according to ITU G. 704
Disabling via Idle channel detection.
Disabling of individual channels via external interfaces ( P, serial and/or UCC
interface)
Disabling Logic
Adaptive Echo Estimation Unit
PCM Input/Output Interface
Figure
3.1.3) of the Adaptive Echo Estimation Unit might be
44
Functional Description
Rev. 2, 2004-07-28
PEB 20954
PEF 20954