PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 46

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

certain controlling functions like the channelwise disabling or A/ -Law conversion can be
operated directly by the hardware without intervention of the microprocessor. This
feature reduces the work load of the processor dramatically.
3.1.9
A Watchdog timer is implemented to reset the on board processor if the software gets
stuck in an undefined state as a result of a faulty operation. A reset condition is met if the
microprocessor fails to write predefined values to the three watchdog registers in the
correct sequence within 2 s. As long as the watchdog is active the SIDEC generates
interrupts and/or reset pulses of 125 s width with a period of 2 s.
3.1.10
The Clock Control supervises and generates all clock signals for proper operation of the
ASIC hardware.
3.1.11
The JTAG (Joint Test Application Group) has been implemented according to IEEE
1149.1. A RAM BIST (Random Access Memory Built In Self Test) is also provided.
3.1.12
The Test Unit controls the background test on disabled channels. A built in self test is
used for testing internal RAMs. This test can be activated after switching on the supply
voltage. The test unit also supervises the Clock Control Unit.
A notebook register allows the check of the P Interface.
Within the Test Unit the registers for background testing of idling channels are
implemented. In this test a pattern is input in the idling channel at Receive in and Send
in and evaluated at the Send out port.
During normal operation the Test Unit supervises functions such as read out of levels,
internal states and coefficients.
Data Sheet
Watchdog Timer
Clock Control
JTAG and RAM BIST
Test
46
Functional Description
Rev. 2, 2004-07-28
PEB 20954
PEF 20954