PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 110

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

FSLIPIV[4:0]
RIALIGN[7:0] ( Addr.: 0DH): Receive input frame alignment, write protected,
Reset value = 00H.
RIALIGN[7:0]
SIALIGN[7:0] (Addr.: 0EH): Send input frame alignment, write protected,
Reset value = 00H.
SIALIGN[7:0]
SOALIGN[7:0] (Addr.: 0FH): Send output frame alignment, write protected,
Reset value = 00H.
SOALIGN[7:0]
Data Sheet
ALIGN[7]
ALIGN[7]
ALIGN[7]
SO
RI
SI
ALIGN[6]
ALIGN[6]
ALIGN[6]
SO
RI
SI
Determines the safety interval around the SYNCO pulse, which
represents the minimum allowed distance between SYNCO and
RFSPN or RFSPF in 2 s steps. If the distance between RFSPN/F
and SYNCO becomes smaller than FSLIPIV[4:0] * 2 s, SYNCO will
jump to the optimal distance of 62.5 s with respect to RFSPN/F
(frame slip). The default value is "01000".
Determines the valid frame bit of the receive input PCM frame
(starting with bit 7 channel 0) at the first falling SCLKI edge, with
which an active SYNCI impulse is detected. (00H = bit 7, channel 0;
FFH = bit 0, channel 31). For explanation see
Determines the valid frame bit of the send input PCM frame (starting
with bit 7 channel 0) at the first falling SCLKI edge, with which an
active SYNCI impulse is detected. (00H = bit 7, channel 0; FFH = bit
0, channel 31). For explanation see
Determines the valid frame bit of the send output PCM frame
(starting with bit 7 channel 0) at the first falling SCLKI edge, with
which an active SYNCI impulse is detected. (00H = bit 7, channel 0;
FFH = bit 0, channel 31). For explanation see
ALIGN[5]
ALIGN[5]
ALIGN[5]
SO
RI
SI
ALIGN[4]
ALIGN[4]
ALIGN[4]
SO
RI
SI
110
ALIGN[3]
ALIGN[3]
ALIGN[3]
SO
RI
SI
ALIGN[2]
ALIGN[2]
Figure
ALIGN[2]
SO
RI
SI
19.
Register Description
Figure
Figure
ALIGN[1]
ALIGN[1]
ALIGN[1]
SO
RI
SI
Rev. 2, 2004-07-28
19.
19.
PEB 20954
PEF 20954
ALIGN[0]
ALIGN[0]
ALIGN[0]
SO
RI
SI