PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 58

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Figure 19
Note: Above values are examples only. PCM frame alignment with respect to the first
detection of an active SYNCI (or SYNCO: If no SYNCI is applied, SYNCO takes over the
part and role of SYNCI) with the falling edge of SCLKI can be configured by writing to the
Data Sheet
(SYNCO)
(SYNCO)
(TMFBO)
(TMFBI)
RO, SO
SYNCI
SYNCI
SCLKI
SCLKI
Timing Characteristics
SCLKI
RI, SI
RO
RO
SO
SO
RI
RI
SI
SI
Bit 2
Bit 2
Bit 4
PCM Signal Timing and Frame Alignment
Bit 0
Bit 6
Bit 6
Bit 3
channel 26
channel 26
channel 2
Bit 1
Bit 1
Bit 7
Bit 2
beginning of phase 2
sampling of RI at the
3
Phase 0
Phase 0
Bit 7
Bit 0
Bit 0
Bit 6
Bit 1
beginning of phase 2
sampling of SI at the
Phase 1
Phase 0
Phase 1
Phase 0
Bit 7
Bit 7
Phase 0
Bit 5
Bit 0
Phase 2
Phase 1
Phase 2
Phase 0
the beginning of phase 2
sampling of RI and SI at
Bit 6
Bit 6
1
Bit 4
channel 26
Bit 7
Phase 3
Phase 2
Phase 3
Phase 1
Phase 1
Bit 5
Bit 5
Phase 1
Bit 3
58
Bit 6
channel 27, frame n-1
channel 27, frame n
Phase 0
Phase 3
Phase 2
Register SIALIGN = D4H,
Register PHALIGN[3:2] = "11"
Bit 4
Bit 4
Register SOALIGN = 19H,
Register PHALIGN[5:4] = "10"
Bit 2
PCM Signal Timing and Frame Alignment
Bit 5
Register RIALIGN = DBH,
Register PHALIGN[1:0] = "00"
Register RIALIGN = DBH,
Register PHALIGN[1:0] = "00"
Phase 1
Phase 3
Phase 2
channel 3
Bit 3
Bit 3
Phase 2
Bit 1
Bit 4
Phase 2
Bit 4
Bit 2
Bit 2
2
Bit 0
Bit 3
Bit 2
Phase 3
Phase 3
Operational Description
Bit 1
Bit 1
Phase 3
Bit 7
Bit 5
Bit 2
channel 27
Bit 0
Bit 0
Bit 6
Bit 1
Rev. 2, 2004-07-28
Bit 3
Bit 3
Bit 7
Bit 7
Bit 1
Bit 5
PEB 20954
PEF 20954